Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_plocf

openfpga_flow/scripts/arch_file_updater.py

@@ -26,6 +26,7 @@ error_codes = {"SUCCESS": 0, "ERROR": 1, "OPTION_ERROR": 2, "FILE_ERROR": 3}
 #####################################################################
 logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO)
 
+
 #####################################################################
 # Upgrade an architecture XML file from version 1.1 syntax to version 1.2
 # Change rules:

openfpga_flow/scripts/io_sequence_visualizer.py

@@ -13,6 +13,7 @@ This example demonstrates the ``OpenFPGA_Arch`` class which parses the
 Author: Ganesh Gore
 
 """
+
 import math
 import svgwrite
 from svgwrite.container import Group

openfpga_flow/scripts/run_fpga_flow.py

@@ -674,9 +674,11 @@ def create_yosys_params():
                 ys_params["READ_HDL_FILE"] += " ".join(
                     [
                         "verific",
+                        (
                             "-L " + ys_params["VERIFIC_SEARCH_LIB"]
                             if "VERIFIC_SEARCH_LIB" in ys_params
-                        else "",
+                            else ""
+                        ),
                         standard,
                         " ".join([shlex.quote(src) for src in sources]),
                         "\n",

requirements.txt

@@ -5,5 +5,5 @@ pyverilog
 
 # Python linter and formatter
 click==8.0.2 # Our version of black needs an older version of click (https://stackoverflow.com/questions/71673404/importerror-cannot-import-name-unicodefun-from-click)
-black==20.8b1
+black==24.3.0
 pylint==2.7.4