diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
new file mode 100644
index 000000000..d5b64a1a5
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
@@ -0,0 +1,198 @@
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+ 10e-12 5e-12 5e-12
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diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile5Clk_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
similarity index 99%
rename from openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile5Clk_40nm.xml
rename to openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
index 9b76b750d..55eeed976 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile5Clk_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml
@@ -5,7 +5,7 @@
- General purpose logic block:
K = 4, N = 4
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
- - 5 operating clocks which can be selected for each logic element
+ - 8 operating clocks which can be selected for each logic element
Details on Modelling:
@@ -56,7 +56,7 @@
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@@ -208,7 +208,7 @@
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