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[Architecture] Bug fix due to adder renaming

This commit is contained in:
tangxifan 2020-09-24 20:42:24 -06:00
parent e4bfa2ef51
commit 0a53a719bd
13 changed files with 26 additions and 26 deletions
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4
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
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@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
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@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12

4
openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
View File

@ -69,8 +69,8 @@
<device_technology device_model_name="logic"/> <device_technology device_model_name="logic"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/> <port type="input" prefix="a" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/> <port type="input" prefix="b" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out"> <delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12 10e-12 5e-12