riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols

This commit is contained in:
tangxifan 2021-09-28 14:20:35 -07:00
parent 4968f0d11f
commit 0a2979d616
4 changed files with 60 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
libopenfpga/libarchopenfpga/src/config_protocol.cpp
View File

@ -45,6 +45,10 @@ CircuitModelId ConfigProtocol::bl_memory_model() const {
return bl_memory_model_;
}
size_t ConfigProtocol::bl_num_banks() const {
return bl_num_banks_;
}
e_blwl_protocol_type ConfigProtocol::wl_protocol_type() const {
return wl_protocol_type_;
}
@ -57,6 +61,10 @@ CircuitModelId ConfigProtocol::wl_memory_model() const {
return wl_memory_model_;
}
size_t ConfigProtocol::wl_num_banks() const {
return wl_num_banks_;
}
/************************************************************************
* Public Mutators
***********************************************************************/
@ -100,6 +108,15 @@ void ConfigProtocol::set_bl_memory_model(const CircuitModelId& memory_model) {
bl_memory_model_ = memory_model;
}
void ConfigProtocol::set_bl_num_banks(const size_t& num_banks) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != bl_protocol_type_) {
VTR_LOG_ERROR("BL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[bl_protocol_type_]);
return;
}
bl_num_banks_ = num_banks;
}
void ConfigProtocol::set_wl_protocol_type(const e_blwl_protocol_type& type) {
if (CONFIG_MEM_QL_MEMORY_BANK != type_) {
VTR_LOG_ERROR("WL protocol type is only applicable for configuration protocol '%d'", CONFIG_PROTOCOL_TYPE_STRING[type_]);
@ -123,3 +140,12 @@ void ConfigProtocol::set_wl_memory_model(const CircuitModelId& memory_model) {
}
wl_memory_model_ = memory_model;
}
void ConfigProtocol::set_wl_num_banks(const size_t& num_banks) {
if (BLWL_PROTOCOL_SHIFT_REGISTER != wl_protocol_type_) {
VTR_LOG_ERROR("WL protocol memory model is only applicable when '%d' is defined", BLWL_PROTOCOL_TYPE_STRING[wl_protocol_type_]);
return;
}
wl_num_banks_ = num_banks;
}

8
libopenfpga/libarchopenfpga/src/config_protocol.h
View File

@ -29,9 +29,11 @@ class ConfigProtocol {
e_blwl_protocol_type bl_protocol_type() const;
std::string bl_memory_model_name() const;
CircuitModelId bl_memory_model() const;
size_t bl_num_banks() const;
e_blwl_protocol_type wl_protocol_type() const;
std::string wl_memory_model_name() const;
CircuitModelId wl_memory_model() const;
size_t wl_num_banks() const;
public: /* Public Mutators */
void set_type(const e_config_protocol_type& type);
void set_memory_model_name(const std::string& memory_model_name);
@ -41,9 +43,11 @@ class ConfigProtocol {
void set_bl_protocol_type(const e_blwl_protocol_type& type);
void set_bl_memory_model_name(const std::string& memory_model_name);
void set_bl_memory_model(const CircuitModelId& memory_model);
void set_bl_num_banks(const size_t& num_banks);
void set_wl_protocol_type(const e_blwl_protocol_type& type);
void set_wl_memory_model_name(const std::string& memory_model_name);
void set_wl_memory_model(const CircuitModelId& memory_model);
void set_wl_num_banks(const size_t& num_banks);
private: /* Internal data */
/* The type of configuration protocol.
* In other words, it is about how to organize and access each configurable memory
@ -62,13 +66,17 @@ class ConfigProtocol {
* - bl/wl_memory_model: defines the circuit model to be used when building shift register chains for BL/WL configuration.
* It must be a valid CCFF circuit model. This is only applicable when shift-register protocol is selected
* for BL or WL.
* - bl/wl_num_banks: defines the number of independent shift register chains (with separated head and tail ports)
* for a given BL protocol per configuration region
*/
e_blwl_protocol_type bl_protocol_type_ = BLWL_PROTOCOL_DECODER;
std::string bl_memory_model_name_;
CircuitModelId bl_memory_model_;
size_t bl_num_banks_;
e_blwl_protocol_type wl_protocol_type_ = BLWL_PROTOCOL_DECODER;
std::string wl_memory_model_name_;
CircuitModelId wl_memory_model_;
size_t wl_num_banks_;
};
#endif

12
libopenfpga/libarchopenfpga/src/read_xml_config_protocol.cpp
View File

@ -68,9 +68,13 @@ void read_xml_bl_protocol(pugi::xml_node& xml_bl_protocol,
config_protocol.set_bl_protocol_type(blwl_protocol_type);
/* Find the memory model, only applicable to shift-registor protocol */
/* only applicable to shift-registor protocol
* - Find the memory model to build shift register chains
* - Find the number of shift register chains for each protocol
*/
if (BLWL_PROTOCOL_SHIFT_REGISTER == blwl_protocol_type) {
config_protocol.set_bl_memory_model_name(get_attribute(xml_bl_protocol, "circuit_model_name", loc_data).as_string());
config_protocol.set_bl_num_banks(get_attribute(xml_bl_protocol, "num_banks", loc_data).as_int(1));
}
}
@ -94,9 +98,13 @@ void read_xml_wl_protocol(pugi::xml_node& xml_wl_protocol,
config_protocol.set_wl_protocol_type(blwl_protocol_type);
/* Find the memory model, only applicable to shift-registor protocol */
/* only applicable to shift-registor protocol
* - Find the memory model to build shift register chains
* - Find the number of shift register chains for each protocol
*/
if (BLWL_PROTOCOL_SHIFT_REGISTER == blwl_protocol_type) {
config_protocol.set_wl_memory_model_name(get_attribute(xml_wl_protocol, "circuit_model_name", loc_data).as_string());
config_protocol.set_wl_num_banks(get_attribute(xml_wl_protocol, "num_banks", loc_data).as_int(1));
}
}

17
libopenfpga/libarchopenfpga/src/write_xml_config_protocol.cpp
View File

@ -26,11 +26,24 @@ void write_xml_config_organization(std::fstream& fp,
openfpga::check_file_stream(fname, fp);
fp << "\t\t" << "<organization";
write_xml_attribute(fp, "type", CONFIG_PROTOCOL_TYPE_STRING[config_protocol.type()]);
write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(config_protocol.memory_model()).c_str());
fp << "/>" << "\n";
/* Output BL/WL protocols */
fp << "\t\t\t" << "<bl";
write_xml_attribute(fp, "protocol", BLWL_PROTOCOL_TYPE_STRING[config_protocol.bl_protocol_type()]);
write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(config_protocol.bl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.bl_num_banks());
fp << "/>" << "\n";
fp << "\t\t\t" << "<wl";
write_xml_attribute(fp, "protocol", BLWL_PROTOCOL_TYPE_STRING[config_protocol.wl_protocol_type()]);
write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(config_protocol.wl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.wl_num_banks());
fp << "/>" << "\n";
fp << "\t" << "</organization>" << "\n";
}
/********************************************************************