From 09ef516de885ba64e1203ece0965cca2d2285b49 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 31 Jan 2022 14:23:13 -0800 Subject: [PATCH] [Script] Tune OpenFPGA shell script to enable testing on relative paths --- ...write_full_testbench_relative_path_example_script.openfpga | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga index e156f743b..74b876e1b 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_relative_path_example_script.openfpga @@ -47,7 +47,7 @@ write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPG # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose --use_relative_path +write_fabric_verilog --file . --explicit_port_mapping --include_timing --print_user_defined_template --verbose --use_relative_path # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -55,7 +55,7 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} --fabric_netlist_file_path fabric_netlists.v # Write the SDC files for PnR backend # - Turn on every options here