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[core] dev

This commit is contained in:
tangxifan 2023-03-01 16:08:15 -08:00
parent 60ff298987
commit 099d9f32f4
2 changed files with 188 additions and 122 deletions
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8
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -331,6 +331,14 @@ std::vector<std::string> ClockNetwork::tree_flatten_taps(
return flatten_taps;
}
ClockTreeId ClockNetwork::find_tree(const std::string& name) const {
auto result = tree_name2id_map_.find(name);
if (result == tree_name2id_map_.end()) {
return ClockTreeId::INVALID();
}
return result->second;
}
ClockSpineId ClockNetwork::find_spine(const std::string& name) const {
auto result = spine_name2id_map_.find(name);
if (result == spine_name2id_map_.end()) {

150
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -975,56 +975,15 @@ static int build_top_module_global_net_for_given_grid_module(
}
/********************************************************************
* Add global ports from grid ports that are defined as global in tile
*annotation
* Add nets between a global port and its sinks at each grid modules
*******************************************************************/
int add_top_module_global_ports_from_grid_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const TileAnnotation& tile_annotation,
static
int build_top_module_global_net_from_grid_modules(
ModuleManager& module_manager, const ModuleId& top_module, const ModulePortId& top_module_port,
const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids) {
int status = CMD_EXEC_SUCCESS;
/* Add the global ports which are NOT yet added to the top-level module
* (in different names than the global ports defined in circuit library
*/
std::vector<BasicPort> global_ports_to_add;
for (const TileGlobalPortId& tile_global_port :
tile_annotation.global_ports()) {
ModulePortId module_port = module_manager.find_module_port(
top_module, tile_annotation.global_port_name(tile_global_port));
/* The global port size is derived from the maximum port size among all the
* tile port defintion */
if (ModulePortId::INVALID() == module_port) {
BasicPort global_port_to_add;
global_port_to_add.set_name(
tile_annotation.global_port_name(tile_global_port));
size_t max_port_size = 0;
for (const BasicPort& tile_port :
tile_annotation.global_port_tile_ports(tile_global_port)) {
max_port_size = std::max(tile_port.get_width(), max_port_size);
}
global_port_to_add.set_width(max_port_size);
global_ports_to_add.push_back(global_port_to_add);
}
}
for (const BasicPort& global_port_to_add : global_ports_to_add) {
module_manager.add_port(top_module, global_port_to_add,
ModuleManager::MODULE_GLOBAL_PORT);
}
/* Add module nets */
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
generate_perimeter_grid_coordinates(grids);
for (const TileGlobalPortId& tile_global_port :
tile_annotation.global_ports()) {
/* Must found one valid port! */
ModulePortId top_module_port = module_manager.find_module_port(
top_module, tile_annotation.global_port_name(tile_global_port));
VTR_ASSERT(ModulePortId::INVALID() != top_module_port);
for (size_t tile_info_id = 0;
tile_info_id <
tile_annotation.global_port_tile_names(tile_global_port).size();
@ -1148,6 +1107,105 @@ int add_top_module_global_ports_from_grid_modules(
}
}
}
return status;
}
/********************************************************************
* Add nets between a global port and its sinks at an entry point of clock tree
*******************************************************************/
int build_top_module_global_net_from_clock_arch_tree(
ModuleManager& module_manager, const ModuleId& top_module, const ModulePortId& top_module_port,
const ClockNetwork& clk_ntwk, const std::string& clk_tree_name, const RRClockSpatialLookup& rr_clock_lookup) {
int status = CMD_EXEC_SUCCESS;
/* Ensure the clock arch tree name is valid */
ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name);
if (!clk_ntwk.valid_tree_id(clk_tree)) {
VTR_LOG("Fail to find a matched clock tree '%s' in the clock architecture definition", clk_tree_name.c_str());
return CMD_EXEC_FATAL_ERROR;
}
/* Ensure the clock tree width matches the global port size */
if (clk_ntwk.tree_width(clk_tree) != module_manager.module_port(top_module, top_module_port).get_width()) {
VTR_LOG("Clock tree '%s' does not have the same width '%lu' as the port '%'s of FPGA top module", clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree), module_manager.module_port(top_module, top_module_port).get_name().c_str());
return CMD_EXEC_FATAL_ERROR;
}
for (ClockTreePinId pin : clk_ntwk.pins(clk_tree)) {
/* TODO: Find the routing resource node of the entry point */
/* TODO: Get the connection block module and instance at the entry point */
/* TODO: Add the module net */
}
return status;
}
/********************************************************************
* Add global ports from grid ports that are defined as global in tile
*annotation
*******************************************************************/
int add_top_module_global_ports_from_grid_modules(
ModuleManager& module_manager, const ModuleId& top_module,
const TileAnnotation& tile_annotation,
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
const vtr::Matrix<size_t>& grid_instance_ids) {
int status = CMD_EXEC_SUCCESS;
/* Add the global ports which are NOT yet added to the top-level module
* (in different names than the global ports defined in circuit library
*/
std::vector<BasicPort> global_ports_to_add;
for (const TileGlobalPortId& tile_global_port :
tile_annotation.global_ports()) {
ModulePortId module_port = module_manager.find_module_port(
top_module, tile_annotation.global_port_name(tile_global_port));
/* The global port size is derived from the maximum port size among all the
* tile port defintion */
if (ModulePortId::INVALID() == module_port) {
BasicPort global_port_to_add;
global_port_to_add.set_name(
tile_annotation.global_port_name(tile_global_port));
size_t max_port_size = 0;
for (const BasicPort& tile_port :
tile_annotation.global_port_tile_ports(tile_global_port)) {
max_port_size = std::max(tile_port.get_width(), max_port_size);
}
global_port_to_add.set_width(max_port_size);
global_ports_to_add.push_back(global_port_to_add);
}
}
for (const BasicPort& global_port_to_add : global_ports_to_add) {
module_manager.add_port(top_module, global_port_to_add,
ModuleManager::MODULE_GLOBAL_PORT);
}
/* Add module nets */
std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
generate_perimeter_grid_coordinates(grids);
for (const TileGlobalPortId& tile_global_port :
tile_annotation.global_ports()) {
/* Must found one valid port! */
ModulePortId top_module_port = module_manager.find_module_port(
top_module, tile_annotation.global_port_name(tile_global_port));
VTR_ASSERT(ModulePortId::INVALID() != top_module_port);
/* There are two cases when building the nets:
* - If the net will go through a dedicated clock tree network, the net will drive an input of a routing block
* - If the net will be directly wired to tiles, the net will drive an input of a tile
*/
if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port).empty()) {
status = build_top_module_global_net_from_clock_arch_tree(module_manager, top_module, top_module_port);
} else {
status = build_top_module_global_net_from_grid_modules(module_manager, top_module, top_module_port, tile_annotation, tile_global_port, vpr_device_annotation, grids, grid_instance_ids);
}
if (status == CMD_EXEC_FATAL_ERROR) {
return status;
}
}
return status;