From c7e1f7d90b1b7ffbea6eb98880dc5829102b0ad0 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 10:17:04 -0600 Subject: [PATCH 1/5] Added explicit_verilog to regression test in a clean way --- .travis/script.sh | 2 +- .../tasks/blif_vpr_flow/config/task.conf | 5 +-- .../tasks/explicit_verilog/config/task.conf | 41 +++++++++++++++++++ 3 files changed, 44 insertions(+), 4 deletions(-) create mode 100644 openfpga_flow/tasks/explicit_verilog/config/task.conf diff --git a/.travis/script.sh b/.travis/script.sh index fa9e95ea8..37e96e1a8 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index cf283f22a..d3fc4fedc 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -64,7 +64,7 @@ vpr_fpga_verilog_print_sdc_analysis= end_flow_with_test= -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT] fix_route_chan_width=300 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= @@ -76,6 +76,5 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_x2p_compact_routing_hierarchy= -vpr_fpga_verilog_explicit_mapping= +#vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf new file mode 100644 index 000000000..be4320161 --- /dev/null +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -0,0 +1,41 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[ARCHITECTURES] +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif + +[SYNTHESIS_PARAM] +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] +fix_route_chan_width=300 +vpr_fpga_verilog_include_icarus_simulator= +vpr_fpga_verilog_formal_verification_top_netlist= +vpr_fpga_verilog_include_timing= +vpr_fpga_verilog_include_signal_init= +vpr_fpga_verilog_print_autocheck_top_testbench= +vpr_fpga_bitstream_generator= +vpr_fpga_verilog_print_user_defined_template= +vpr_fpga_verilog_print_report_timing_tcl= +vpr_fpga_x2p_compact_routing_hierarchy= +vpr_fpga_verilog_explicit_mapping= +end_flow_with_test= From db059af8b80cb28621bf317ed977dfc34a9914ce Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 13:33:28 -0600 Subject: [PATCH 2/5] Lighten the regression test --- .../tasks/blif_vpr_flow/config/task.conf | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index d3fc4fedc..c54ce8403 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -63,18 +63,3 @@ vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT] -fix_route_chan_width=300 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= From 95596bb4f825c740f0d3929c5dad36d520227a54 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 13:50:01 -0600 Subject: [PATCH 3/5] Correction on the cb vs sb corrdinator. Does not fix the problem though --- .../vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 96aea8d43..38d705461 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -953,13 +953,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Print each INPUT Pins of a grid */ if (true == is_explicit_mapping) { if (RIGHT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type) + 1, unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (TOP == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (LEFT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (BOTTOM == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, From 6f7023658efe50ba18d76c559066fe15a33673f7 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 3 Oct 2019 14:59:04 -0600 Subject: [PATCH 4/5] Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though" This reverts commit 95596bb4f825c740f0d3929c5dad36d520227a54. --- .../vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 38d705461..96aea8d43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -953,13 +953,13 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Print each INPUT Pins of a grid */ if (true == is_explicit_mapping) { if (RIGHT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type) + 1, unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (TOP == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (LEFT == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type) + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } else if (BOTTOM == side_manager.get_side()) { - fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_cb_x(cb_type), unique_mirror.get_cb_y(cb_type), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); } } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, From 027272c976850945c7c714cfee704bc88704efec Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Sat, 5 Oct 2019 12:10:55 -0600 Subject: [PATCH 5/5] Faster regression test --- .travis/script.sh | 2 +- openfpga_flow/tasks/explicit_verilog/config/task.conf | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index 37e96e1a8..73e2a1ed2 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -18,5 +18,5 @@ end_section "OpenFPGA.build" start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd - -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 2 +python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow tileable_routing explicit_verilog --maxthreads 3 end_section "OpenFPGA.TaskTun" diff --git a/openfpga_flow/tasks/explicit_verilog/config/task.conf b/openfpga_flow/tasks/explicit_verilog/config/task.conf index be4320161..0634a32c5 100644 --- a/openfpga_flow/tasks/explicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/explicit_verilog/config/task.conf @@ -16,6 +16,7 @@ fpga_flow=vpr_blif [ARCHITECTURES] arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +#arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -27,7 +28,7 @@ bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Test_Modes/test_ bench0_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_EXPLICIT_MAPPING_COMPACT] -fix_route_chan_width=300 +min_route_chan_width=1.3 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= vpr_fpga_verilog_include_timing= @@ -39,3 +40,4 @@ vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_x2p_compact_routing_hierarchy= vpr_fpga_verilog_explicit_mapping= end_flow_with_test= +