diff --git a/docs/source/manual/openfpga_shell/openfpga_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands.rst
index 1ac4ed69b..6e2f0e490 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands.rst
@@ -172,6 +172,8 @@ FPGA-Verilog
 
   - ``--reference_benchmark_file_path`` Must specify the reference benchmark Verilog file if you want to output any testbenches
 
+  - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to memory bank and frame-based configuration protocols. When enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
+
   - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 
   - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification