From 0902d1e75a646f3e920673fa5122dbbf32bff6b9 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 13 Jun 2019 18:38:46 -0600 Subject: [PATCH] c++ string is not working, use char which is stable --- .../Blif/Test_Modes/test_modes.power | 172 ------------------ vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 88 +++++---- .../SRC/fpga_x2p/base/rr_blocks_naming.cpp | 6 - .../SRC/fpga_x2p/verilog/verilog_primitives.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 22 +-- vpr7_x2p/vpr/VerilogNetlists/ff.v | 2 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 7 files changed, 65 insertions(+), 229 deletions(-) delete mode 100644 fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power diff --git a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power b/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power deleted file mode 100644 index b9730e324..000000000 --- a/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.power +++ /dev/null @@ -1,172 +0,0 @@ ------------------------------------ Summary ------------------------------------ -Circuit: /research/ece/lnis/USERS/tang/github/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes -Architecture: k6_N10_sram_chain_HC_template.xml -Technology (nm): 45 -Voltage: 0.90 -Temperature: 85 -Critical Path: 5.8141e-09 -Size of FPGA: 2 x 2 -Channel Width: 200 - ------------------------------------ Warnings ----------------------------------- -No transistor counter function for BLIF model: .frac_lut6 -No transistor counter function for BLIF model: .subckt adder -No transistor counter function for BLIF model: .subckt shift -Attempted to search for a transistor with a capacitance smaller than the smallest in the technology file. - -No dynamic power defined for BLIF model: .subckt adder -No leakage power defined for BLIF model: .subckt adder -No dynamic power defined for BLIF model: .frac_lut6 -No leakage power defined for BLIF model: .frac_lut6 -No dynamic power defined for BLIF model: .subckt shift -No leakage power defined for BLIF model: .subckt shift - -------------------------------- Power Breakdown -------------------------------- -Component Power (W) %-Total %-Dynamic Method - -Total 0.0002701 1 0.7897 - Routing 0.0001289 0.4773 0.7668 - Switch Box 2.212e-05 0.08191 0 - Connection Box 0.0001068 0.3954 0.9256 - Global Wires 0 0 -nan - PB Types 8.066e-05 0.2986 0.6884 - Primitives 4.913e-05 0.1819 0.8837 - Interc Structures 8.866e-06 0.03283 0.5489 - Buffers and Wires 2.266e-05 0.08389 0.3197 - Other Estimation Methods 0 0 -nan - Clock 6.051e-05 0.224 0.9736 - ----------------------------- Power Breakdown by PB ----------------------------- -This sections provides a detailed breakdown of power usage by PB (physical -block). For each PB, the power is listed, which is the sum power of all -instances of the block. It also indicates its percentage of total power (entire -FPGA), as well as the percentage of its power that is dynamic (vs. static). It -also indicates the method used for power estimation. - -The data includes: - Modes: When a pb contains multiple modes, each mode is listed, with - its power statistics. - Bufs/Wires: Power of all local buffers and local wire switching - (transistor-level estimation only). - Interc: Power of local interconnect multiplexers (transistor- - level estimation only) - -Description of Estimation Methods: - Transistor Auto-Size: Transistor-level power estimation. Local buffers and - wire lengths are automatically sized. This is the default estimation - method. - Transistor Specify-Size: Transistor-level power estimation. Local buffers - and wire lengths are only inserted where specified by the user in the - architecture file. - Pin-Toggle: Dynamic power is calculated using enery-per-toggle of the PB - input pins. Static power is absolute. - C-Internal: Dynamic power is calculated using an internal equivalent - capacitance for PB type. Static power is absolute. - Absolute: Dynamic and static power are absolutes from the architecture file. - Sum of Children: Power of PB is only the sum of all child PBs; interconnect - between the PB and its children is ignored. - Ignore: Power of PB is ignored. - - -Component Power (W) %-Total %-Dynamic Method - -io 0 0 -nan Ignore -clb 8.066e-05 0.2986 0.6884 Transistor Auto-Size - Bufs/Wires 1.43e-05 0.05294 0.2804 - Interc: 8.462e-06 0.03133 0.542 - crossbar0 3.015e-06 0.01116 0.5188 - crossbar1 3.264e-06 0.01208 0.5568 - crossbar2 1.076e-06 0.003984 0.5484 - crossbar3 8.245e-07 0.003053 0.5364 - crossbar4 0 0 -nan - crossbar5 0 0 -nan - clks 0 0 -nan - carry_in 2.821e-07 0.001045 0.6112 - fle 5.79e-05 0.2144 0.8106 Transistor Auto-Size - Bufs/Wires 6.769e-06 0.02506 0.3446 - Mode:fle_phy 3.361e-05 0.1244 0.9139 - Interc: 0 0 -nan - direct_clk 0 0 -nan - mux1 0 0 -nan - mux2 0 0 -nan - frac_logic 3.388e-07 0.001254 0 Transistor Auto-Size - Bufs/Wires 3.388e-07 0.001254 0 - Interc: 0 0 -nan - mux1 0 0 -nan - mux2 0 0 -nan - frac_lut6 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - adder_phy 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - ff_phy 3.327e-05 0.1232 0.9232 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:n2_lut5 1.741e-05 0.06444 0.7925 - Interc: 0 0 -nan - lut5inter 1.741e-05 0.06444 0.7925 Transistor Auto-Size - Bufs/Wires 5.658e-07 0.002095 0.6977 - Interc: 0 0 -nan - complete1 0 0 -nan - ble5 1.684e-05 0.06235 0.7956 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:blut5 1.12e-05 0.04146 0.8091 - Interc: 0 0 -nan - flut5 1.12e-05 0.04146 0.8091 Transistor Auto-Size - Bufs/Wires 2.007e-07 0.000743 0.7628 - Interc: 2.646e-07 0.0009797 0.684 - mux1 2.646e-07 0.0009797 0.684 - lut5 1.655e-06 0.006127 0.2417 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:wire 0 0 -nan - Interc: 0 0 -nan - complete:lut5 0 0 -nan - Mode:lut5 1.655e-06 0.006127 0.2417 - Interc: 0 0 -nan - lut 1.655e-06 0.006127 0.2417 Transistor Auto-Size - Bufs/Wires 0 0 -nan - ff 9.079e-06 0.03361 0.9173 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:arithmetic 5.641e-06 0.02088 0.7689 - Interc: 0 0 -nan - arithmetic 5.641e-06 0.02088 0.7689 Transistor Auto-Size - Bufs/Wires 3.732e-07 0.001382 0.7081 - Interc: 1.399e-07 0.0005179 0.708 - sumout 1.399e-07 0.0005179 0.708 - lut4 7.913e-07 0.00293 0 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:wire 0 0 -nan - Interc: 0 0 -nan - complete:lut4 0 0 -nan - Mode:lut4 7.913e-07 0.00293 0 - Interc: 0 0 -nan - lut 7.913e-07 0.00293 0 Transistor Auto-Size - Bufs/Wires 0 0 -nan - adder 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - ff 4.336e-06 0.01606 0.9163 Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:n1_lut6 0 0 -nan - Interc: 0 0 -nan - ble6 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - Interc: 0 0 -nan - mux1 0 0 -nan - lut6 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:wire 0 0 -nan - Interc: 0 0 -nan - complete:lut6 0 0 -nan - Mode:lut6 0 0 -nan - Interc: 0 0 -nan - lut 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - ff 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - Mode:shift_register 1.134e-07 0.0004199 0.7826 - Interc: 0 0 -nan - ble_shift 1.134e-07 0.0004199 0.7826 Transistor Auto-Size - Bufs/Wires 1.134e-07 0.0004199 0.7826 - Interc: 0 0 -nan - direct3 0 0 -nan - ff 0 0 -nan Transistor Auto-Size - Bufs/Wires 0 0 -nan - diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index a30aded14..cb8de00d3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -1,5 +1,5 @@ #include -#include +#include #include #include @@ -1345,55 +1345,71 @@ const char* RRGSB::gen_cb_verilog_routing_track_name(t_rr_type cb_type, std::string y_str = std::to_string(get_cb_y(cb_type)); std::string track_id_str = std::to_string(track_id); - std::ostringstream oss; - oss << cb_name << "_" << x_str << "__" << y_str << "__midout_" << track_id_str << "_"; - std::string ret = oss.str(); - - return ret.c_str(); + char* ret = (char*)my_malloc(sizeof(char)* + ( cb_name.length() + 1 + + x_str.length() + 2 + + y_str.length() + 9 + + track_id_str.length() + 1 + + 1)); + sprintf (ret, "%s_%s__%s__midout_%s_", + cb_name.c_str(), x_str.c_str(), y_str.c_str(), track_id_str.c_str()); + return ret; } const char* RRGSB::gen_sb_verilog_module_name() const { std::string x_str = std::to_string(get_sb_x()); std::string y_str = std::to_string(get_sb_y()); - std::ostringstream oss; - oss << "sb_" << x_str << "__" << y_str << "_" ; - std::string ret = oss.str(); + char* ret = (char*)my_malloc(sizeof(char)* + ( 2 + 1 + + x_str.length() + 2 + + y_str.length() + 1 + + 1)); + sprintf (ret, "sb_%s__%s_", + x_str.c_str(), y_str.c_str()); - return ret.c_str(); + return ret; } const char* RRGSB::gen_sb_verilog_instance_name() const { - - std::ostringstream oss; - oss << gen_sb_verilog_module_name() << "_0_" ; - std::string ret = oss.str(); + char* ret = (char*)my_malloc(sizeof(char)* + ( strlen(gen_sb_verilog_module_name()) + 3 + + 1)); + sprintf (ret, "%s_0_", + gen_sb_verilog_module_name()); - return ret.c_str(); + return ret; } /* Public Accessors Verilog writer */ const char* RRGSB::gen_sb_verilog_side_module_name(enum e_side side, size_t seg_id) const { Side side_manager(side); + std::string prefix_str(gen_sb_verilog_module_name()); std::string seg_id_str(std::to_string(seg_id)); std::string side_str(side_manager.to_string()); - std::ostringstream oss; - oss << gen_sb_verilog_module_name() << "_" << side_str << "_seg_" << "_" << seg_id_str << "_" ; - std::string ret = oss.str(); + char* ret = (char*)my_malloc(sizeof(char)* + ( prefix_str.length() + 1 + + side_str.length() + 5 + + seg_id_str.length() + 1 + + 1)); + sprintf (ret, "%s_%s_seg_%s_", + prefix_str.c_str(), side_str.c_str(), seg_id_str.c_str()); - return ret.c_str(); + return ret; } const char* RRGSB::gen_sb_verilog_side_instance_name(enum e_side side, size_t seg_id) const { + std::string prefix_str = gen_sb_verilog_side_module_name(side, seg_id); + char* ret = (char*)my_malloc(sizeof(char)* + ( prefix_str.length() + 3 + + 1)); + sprintf (ret, "%s_0_", + prefix_str.c_str()); - std::ostringstream oss; - oss << gen_sb_verilog_side_module_name(side, seg_id) << "_0_" ; - std::string ret = oss.str(); - - return ret.c_str(); + return ret; } /* Public Accessors Verilog writer */ @@ -1405,23 +1421,29 @@ const char* RRGSB::gen_cb_verilog_module_name(t_rr_type cb_type) const { std::string x_str = std::to_string(get_cb_x(cb_type)); std::string y_str = std::to_string(get_cb_y(cb_type)); - std::ostringstream oss; - oss << prefix_str << "_" << x_str << "__" << y_str << "_" ; - std::string ret = oss.str(); + char* ret = (char*)my_malloc(sizeof(char)* + ( prefix_str.length() + 1 + + x_str.length() + 2 + + y_str.length() + 1 + + 1)); + sprintf (ret, "%s_%s__%s_", + prefix_str.c_str(), x_str.c_str(), y_str.c_str()); - return ret.c_str(); + return ret; } const char* RRGSB::gen_cb_verilog_instance_name(t_rr_type cb_type) const { /* check */ assert (validate_cb_type(cb_type)); - std::ostringstream oss; - oss << gen_cb_verilog_module_name(cb_type) << "_0_" ; - std::string ret = oss.str(); - - return ret.c_str(); + std::string prefix_str = gen_cb_verilog_module_name(cb_type); + char* ret = (char*)my_malloc(sizeof(char)* + (prefix_str.length() + 3 + + 1)); + sprintf (ret, "%s_0_", + prefix_str.c_str()); + return ret; } /* Public mutators */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp index 93530e5f6..2a7f86fb3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks_naming.cpp @@ -10,10 +10,8 @@ char* convert_cb_type_to_string(t_rr_type chan_type) { switch(chan_type) { case CHANX: return "cbx"; - break; case CHANY: return "cby"; - break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", @@ -26,10 +24,8 @@ char* convert_chan_type_to_string(t_rr_type chan_type) { switch(chan_type) { case CHANX: return "chanx"; - break; case CHANY: return "chany"; - break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of channel!\n", @@ -42,10 +38,8 @@ char* convert_chan_rr_node_direction_to_string(enum PORTS chan_rr_node_direction switch(chan_rr_node_direction) { case IN_PORT: return "in"; - break; case OUT_PORT: return "out"; - break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid type of port!\n", __FILE__, __LINE__); exit(1); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 6e68fb13b..3b8001a95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -235,7 +235,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, /* assert */ num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); /* print ports --> input ports */ - dump_verilog_pb_type_bus_ports(fp, port_prefix, 0, prim_pb_type, FALSE, TRUE); + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index a54edc7e0..9d049bc70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -3029,7 +3029,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); int drive_node_index = rr_gsb.get_cb_chan_node_index(cb_type, drive_rr_nodes[inode]); assert (-1 != drive_node_index); - fprintf(fp, "%s;", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, drive_node_index)); + fprintf(fp, "%s;\n", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, drive_node_index)); input_cnt++; } assert(input_cnt == mux_size); @@ -4076,13 +4076,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, DeviceCoordinator cb_range = device_rr_gsb.get_gsb_range(); /* X - channels [1...nx][0..ny]*/ - for (int iy = 0; iy < (ny + 1); iy++) { - for (int ix = 1; ix < (nx + 1); ix++) { - for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { - const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); - } - } + for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { + const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); } /* TODO: when we follow a tile organization, * updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */ @@ -4094,13 +4090,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, } /* Y - channels [1...ny][0..nx]*/ - for (int ix = 0; ix < (nx + 1); ix++) { - for (int iy = 1; iy < (ny + 1); iy++) { - for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { - const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY); - } - } + for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { + const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY); } for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { diff --git a/vpr7_x2p/vpr/VerilogNetlists/ff.v b/vpr7_x2p/vpr/VerilogNetlists/ff.v index b52ba4078..c01097048 100644 --- a/vpr7_x2p/vpr/VerilogNetlists/ff.v +++ b/vpr7_x2p/vpr/VerilogNetlists/ff.v @@ -5,7 +5,7 @@ // Coder : Xifan TANG //----------------------------------------------------- //------ Include defines: preproc flags ----- -`include "OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v" +`include "/research/ece/lnis/USERS/tang/github/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog/SRC/fpga_defines.v" module static_dff ( /* Global ports go first */ input set, // set input diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 21602c821..586898bb5 100644 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -4,7 +4,7 @@ # Set variables # For FPGA-Verilog ONLY benchmark="test_modes" -OpenFPGA_path="OPENFPGAPATHKEYWORD" +OpenFPGA_path="/research/ece/lnis/USERS/tang/github/OpenFPGA" verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$PWD" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml"