diff --git a/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga
index b66992eb7..3f0b84485 100644
--- a/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/wire_lut_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results on --absorb_buffer_luts off
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --skip_sync_clustering_and_routing_results off --absorb_buffer_luts off --constant_net_method route
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
@@ -15,9 +15,6 @@ link_openfpga_arch --sort_gsb_chan_node_in_edges
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
 # Apply fix-up to Look-Up Table truth tables based on packing results
 lut_truth_table_fixup