debugging bibtex

docs/requirements.txt

@@ -0,0 +1,15 @@
+#Python requirements file for building documentation
+# used by Read The Docs to install python required 
+# modules with pip.
+
+# Support Markdown
+#recommonmark
+
+#Handle references in bibtex format
+sphinxcontrib-bibtex
+
+#Work-around bug "AttributeError: 'Values' object has no attribute 'character_level_inline_markup'" with docutils 0.13.1
+#See:
+#  * https://github.com/sphinx-doc/sphinx/issues/3951
+#  * https://sourceforge.net/p/docutils/bugs/304/
+#docutils>=0.14

docs/source/conf.py

@@ -24,11 +24,11 @@ import sphinx_rtd_theme
 #html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
 
 # Import sphinxcontrib.bibtex
-#have_sphinxcontrib_bibtex = True
-#try:
-#    import sphinxcontrib.bibtex
-#except ImportError:
-#    have_sphinxcontrib_bibtex = False
+have_sphinxcontrib_bibtex = True
+try:
+    import sphinxcontrib.bibtex
+except ImportError:
+    have_sphinxcontrib_bibtex = False
 
 # -- Project information -----------------------------------------------------
 

docs/source/motivation.rst

@@ -1,9 +1,9 @@
 Motivation
 ==========
 
-The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999, JGoeders_FPT_2012` . Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages on generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
+The built-in timing and power analysis engines of VPR are based on analytical models :cite:`VBetz_Book_1999, JGoeders_FPT_2012`. Analytical model-based analysis can promise accuracy only on a limited number of circuit designs for which the model is valid. As the technology advancements create more opportunities on circuit designs and FPGA architectures, the analytical power model require to be updated to follow the new trends. However, without referring to simulation results, the analytical power models cannot prove their accuracy. SPICE simulators have the advantages on generality and accuracy over analytical models. For this reason, SPICE simulation results are often selected to check the accuracy of analytical models. Therefore, there is a strong need for a simulation-based power analysis approach for FPGAs, which can support general circuit designs.
 
-It motivates us to develop FPGA-SPICE, an add-on for the current State-of-Art FPGA architecture exploration tools, VPR :cite:`JRose_FPGA_2012` .
+It motivates us to develop FPGA-SPICE, an add-on for the current State-of-Art FPGA architecture exploration tools, VPR :cite:`JRose_FPGA_2012`.
 FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA architectures supported by VPR. The SPICE netlists and testbenches are generated according to the placement and routing results of VPR. As a result, SPICE simulator can be used to perform accurate delay and power analysis. The SPICE simulation results are useful in three aspects: (1) it can provide accurate power analysis; (2) it helps improving the accuracy of built-in analytical models; and moreover (3) it creates opportunities in developing novel analytical models.
 
 SPICE modeling for FPGA architectures requires a detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we develop an extension on the VPR architectural description language in order to model the transistor-level circuit designs.