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[FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly

This commit is contained in:
tangxifan 2022-02-23 15:33:24 -08:00
parent 484c60b6ab
commit 086642d134
1 changed files with 4 additions and 0 deletions
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4
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
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@ -235,6 +235,10 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
} else { } else {
VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name); VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name);
std::vector<size_t> default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); std::vector<size_t> default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id));
/* For configuration done signals, we should enable them in preconfigured wrapper */
if (fabric_global_ports.global_port_is_config_enable(global_port_id)) {
default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id));
}
print_verilog_wire_constant_values(fp, module_global_pin, default_values); print_verilog_wire_constant_values(fp, module_global_pin, default_values);
} }
} }