From 07f05cc9425b2e0ee2cfe3acaef0bc7daf733bc4 Mon Sep 17 00:00:00 2001 From: bbleaptrot <35536624+bbleaptrot@users.noreply.github.com> Date: Tue, 23 Mar 2021 17:16:27 -0600 Subject: [PATCH] Update user_defined_temp_tutorial.rst Update to remove two images that were hard to read on the webpage and replace with code blocks --- .../user_defined_temp_tutorial.rst | 77 +++++++++++++------ 1 file changed, 55 insertions(+), 22 deletions(-) diff --git a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst index 40b1e9452..27f4289de 100644 --- a/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst +++ b/docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst @@ -5,22 +5,16 @@ Introduction and Setup **In this tutorial, we will** - Provide motivation for generating the user_defined_templates.v verilog file - Go through a generated user_defined_templates.v file to demonstrate how to use it -Through this example, we will motivate and show how to use the user_defined_templates.v file. +Through this example, we will motivate and show how to use the ``user_defined_templates.v`` file. For this examaple, we are using a modified version of the hard adder task that comes with OpenFPGA. To follow along, go to the root directory of OpenFPGA and enter: ``vi openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml`` -Go to line 187 and remove the path for the verilog_netlist. The modified file should look like :numref:`fig_modified_arch_file`. +Go to line 187 and replace it with: -.. _fig_modified_arch_file: - -.. figure:: ./figures/modified_arch_file.png - :scale: 50% - - -The Modified k6_frac_N10_adder_chain_40nm_openfpga.xml File +```` Motivation ~~~~~~~~~~ @@ -36,17 +30,17 @@ Running this command should fail and produce output similar to :numref:`fig_Erro :scale: 50% -Errors Created by k6_frac_N10_adder_chain_40nm_openfpga.xml File Modification +Errors Created by ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` File Modification -This command failed during the verification step because the path to the module definition for ADDF is missing. In our architecture file, user-defined verilog modules are those ```` with the key term verilog_netlist. The user_defined_templates.v file provides a module template for incorporating Hard IPs with no external library into the architecture. +This command failed during the verification step because the path to the module definition for ADDF is missing. In our architecture file, user-defined verilog modules are those ```` with the key term verilog_netlist. The `user_defined_templates.v` file provides a module template for incorporating Hard IPs with no external library into the architecture. Fixing the Error ~~~~~~~~~~~~~~~~ -This error can be resolved by putting the following line back into the k6_frac_N10_adder_chain_40nm_openfpga.xml file at line 187 in the verilog_netlist location: +This error can be resolved by putting the following line back into the ``k6_frac_N10_adder_chain_40nm_openfpga.xml`` file at line 187 in the verilog_netlist location: ``${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/adder.v`` -The above line provides a path to generate the user_defined_templates.v file. +The above line provides a path to generate the ``user_defined_templates.v`` file. Now we can return to the root directory and run this command again: ``python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs`` @@ -58,19 +52,58 @@ The `user_defined_templates.v`_ file can be found starting from the root directo ``vi openfpga_flow/tasks/fpga_verilog/adder/hard_adder/latest/k6_frac_N10_tileable_adder_chain_40nm/and2/MIN_ROUTE_CHAN_WIDTH/SRC/sub_module/user_defined_templates.v`` This file contains user-defined verilog modules that are found in the openfpga_cell_library with ports declaration (compatible with other netlists that are auto-generated by OpenFPGA) but without functionality. The file is used as a reference for engineers to check what is the port sequence required by top-level verilog netlists. This file can be included in simulation only if there are modifications to the file. -To implement our own ADDF module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). The file should resemble :numref:`fig_modified_templates_file` +To implement our own ADDF module, we need to remove all other module definitions (they are already defined elsewhere and will cause an error if left in). Replace the ``user_defined_templates.v`` file with the following: -.. _fig_modified_templates_file: +``//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: Template for user-defined Verilog modules +// Author: Xifan TANG +// Organization: University of Utah +// Date: Fri Mar 19 10:05:32 2021 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps -.. figure:: ./figures/modified_user_defined_templates_file.png - :scale: 50% - - -The Finished user_defined_templates.v File -We can now link this user_defined_templates.v into k6_frac_N10_adder_chain_40nm_openfpga.xml. -.. note:: Be sure to select the run where you modified the user_defined_templates.v! +// ----- Template Verilog module for ADDF ----- +//----- Default net type ----- +`default_nettype none + +// ----- Verilog module for ADDF ----- +module ADDF(A, + B, + CI, + SUM, + CO); +//----- INPUT PORTS ----- +input [0:0] A; +//----- INPUT PORTS ----- +input [0:0] B; +//----- INPUT PORTS ----- +input [0:0] CI; +//----- OUTPUT PORTS ----- +output [0:0] SUM; +//----- OUTPUT PORTS ----- +output [0:0] CO; + +//----- BEGIN wire-connection ports ----- +//----- END wire-connection ports ----- + + +//----- BEGIN Registered ports ----- +//----- END Registered ports ----- + +// ----- Internal logic should start here ----- + assign SUM = A ^ B ^ CI; + assign CO = (A & B) | (A & CI) | (B & CI); +// ----- Internal logic should end here ----- +endmodule +// ----- END Verilog module for ADDF -----`` + +We can now link this ``user_defined_templates.v`` into ``k6_frac_N10_adder_chain_40nm_openfpga.xml``. + +.. note:: Be sure to select the run where you modified the ``user_defined_templates.v``! From the OpenFPGA root directory, run: