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[core] clang syntax

This commit is contained in:
tangxifan 2024-11-13 16:03:06 -08:00
parent 0518058fb1
commit 07cbfa612e
8 changed files with 13 additions and 13 deletions
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2
libs/libopenfpgacapnproto/gen/unique_blocks_uxsdcxx.capnp
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@ -6,7 +6,7 @@
# Input file: /home/xifan/github/OpenFPGA/libs/libopenfpgacapnproto/gen/unique_blocks.xsd
# md5sum of input file: 1db9d740309076fa51f61413bae1e072
@0xdae3749fdf603d4b;
@0xdda3f3f93e497b0c;
using Cxx = import "/capnp/c++.capnp";
$Cxx.namespace("ucap");

4
openfpga/src/fabric/build_fabric_io_location_map.cpp
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@ -76,7 +76,7 @@ static IoLocationMap build_fabric_fine_grained_io_location_map(
if (size_t(phy_tile_type->capacity) !=
module_manager.io_children(child).size()) {
VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
phy_tile_type->name, coord.x(), coord.y(),
phy_tile_type->name.c_str(), coord.x(), coord.y(),
phy_tile_type->capacity,
module_manager.io_children(child).size());
}
@ -211,7 +211,7 @@ static IoLocationMap build_fabric_tiled_io_location_map(
if (size_t(phy_tile_type->capacity) !=
module_manager.io_children(tile_child).size()) {
VTR_LOG("%s[%ld][%ld] capacity: %d while io_child number is %d",
phy_tile_type->name, coord.x(), coord.y(),
phy_tile_type->name.c_str(), coord.x(), coord.y(),
phy_tile_type->capacity,
module_manager.io_children(tile_child).size());
}

4
openfpga/src/fpga_spice/spice_grid.cpp
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@ -290,10 +290,10 @@ static void print_spice_physical_tile_netlist(
if (true == is_io_type(phy_block_type)) {
SideManager side_manager(border_side);
VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
spice_fname.c_str(), phy_block_type->name, side_manager.c_str());
spice_fname.c_str(), phy_block_type->name.c_str(), side_manager.c_str());
} else {
VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
spice_fname.c_str(), phy_block_type->name);
spice_fname.c_str(), phy_block_type->name.c_str());
}
/* Create the file stream */

4
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -315,10 +315,10 @@ static void print_verilog_physical_tile_netlist(
SideManager side_manager(border_side);
VTR_LOG(
"Writing Verilog Netlist '%s' for physical tile '%s' at %s side ...",
verilog_fpath.c_str(), phy_block_type->name, side_manager.c_str());
verilog_fpath.c_str(), phy_block_type->name.c_str(), side_manager.c_str());
} else {
VTR_LOG("Writing Verilog Netlist '%s' for physical_tile '%s'...",
verilog_fpath.c_str(), phy_block_type->name);
verilog_fpath.c_str(), phy_block_type->name.c_str());
}
/* Create the file stream */

2
openfpga/src/repack/lb_router.cpp
View File

@ -441,7 +441,7 @@ bool LbRouter::try_route(const LbRRGraph& lb_rr_graph,
VTR_LOG(
"Net %lu '%s' is impossible to route within proposed %s cluster\n",
inet, atom_nlist.net_name(lb_net_atom_net_ids_[NetId(inet)]).c_str(),
lb_type_->name);
lb_type_->name.c_str());
VTR_LOG("\tNet source pin:\n");
for (size_t isrc = 0; isrc < lb_net_sources_[NetId(inet)].size();
++isrc) {

2
openfpga/src/tile_direct/build_tile_direct.cpp
View File

@ -355,7 +355,7 @@ static void report_direct_from_port_and_to_port_mismatch(
"From_port '%s[%lu:%lu] of direct '%s' does not match to_port "
"'%s[%lu:%lu]'!\n",
from_tile_port.get_name().c_str(), from_tile_port.get_lsb(),
from_tile_port.get_msb(), vpr_direct.name, to_tile_port.get_name().c_str(),
from_tile_port.get_msb(), vpr_direct.name.c_str(), to_tile_port.get_name().c_str(),
to_tile_port.get_lsb(), to_tile_port.get_msb());
}

6
openfpga/src/utils/check_tile_annotation.cpp
View File

@ -181,7 +181,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str(),
physical_tile.name, tile_port.name);
physical_tile.name.c_str(), tile_port.name);
num_err++;
}
@ -196,7 +196,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str(),
physical_tile.name, tile_port.name);
physical_tile.name.c_str(), tile_port.name);
num_err++;
}
@ -211,7 +211,7 @@ static int check_tile_annotation_conflicts_with_physical_tile(
required_tile_port.get_name().c_str(),
required_tile_port.get_lsb(), required_tile_port.get_msb(),
tile_annotation.global_port_name(tile_global_port).c_str(),
physical_tile.name, tile_port.name, pin_Fc);
physical_tile.name.c_str(), tile_port.name, pin_Fc);
}
found_matched_physical_tile_port++;

2
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -72,7 +72,7 @@ float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin) {
}
/* Every pin should have a Fc, give a wrong value */
VTR_LOGF_ERROR(__FILE__, __LINE__, "Fail to find the Fc for %s.pin[%lu]\n",
type->name, pin);
type->name.c_str(), pin);
exit(1);
}