riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

now use openfpga tokenizer to trim command line string in openfpga shell

This commit is contained in:
tangxifan 2020-04-13 11:08:31 -06:00
parent 7ba3e27371
commit 07a384e440
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
libopenfpga/libopenfpgashell/src/shell.tpp
View File

@ -311,9 +311,9 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
/* Remove the space at the end of the line /* Remove the space at the end of the line
* So that we can check easily if there is a continued line in the end * So that we can check easily if there is a continued line in the end
*/ */
cmd_part.erase(std::find_if(cmd_part.rbegin(), cmd_part.rend(), [](int ch) { StringToken cmd_part_tokenizer(cmd_part);
return !std::isspace(ch); cmd_part_tokenizer.rtrim(std::string(" "));
}).base(), cmd_part.end()); cmd_part = cmd_part_tokenizer.data();
/* If the line ends with '\', this is a continued line, parse the next until it ends */ /* If the line ends with '\', this is a continued line, parse the next until it ends */
if ('\\' == cmd_part.back()) { if ('\\' == cmd_part.back()) {
@ -334,9 +334,9 @@ void Shell<T>::run_script_mode(const char* script_file_name, T& context) {
} }
/* Remove the space at the beginning of the line */ /* Remove the space at the beginning of the line */
cmd_line.erase(cmd_line.begin(), std::find_if(cmd_line.begin(), cmd_line.end(), [](int ch) { StringToken cmd_line_tokenizer(cmd_line);
return !std::isspace(ch); cmd_line_tokenizer.ltrim(std::string(" "));
})); cmd_line = cmd_line_tokenizer.data();
/* Process the command only when the full command line in ended */ /* Process the command only when the full command line in ended */
if (!cmd_line.empty()) { if (!cmd_line.empty()) {

4
openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga
View File

@ -41,7 +41,9 @@ build_fabric_bitstream --verbose
# Write the Verilog netlist for FPGA fabric # Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist # - Enable the use of explicit port mapping in Verilog netlist
write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \
--explicit_port_mapping --include_timing --include_signal_init \
--support_icarus_simulator --print_user_defined_template --verbose
# Write the Verilog testbench for FPGA fabric # Write the Verilog testbench for FPGA fabric
# - We suggest the use of same output directory as fabric Verilog netlists # - We suggest the use of same output directory as fabric Verilog netlists