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Merge remote-tracking branch 'upstream/master' into update_from_upstream

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nadeemyaseen-rs 2021-11-25 00:00:22 +05:00
parent 773d45258a 1fd9367ae9
commit 06fb4b0ece
2 changed files with 38 additions and 39 deletions
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75
openfpga_flow/tasks/quicklogic_tests/flow_test/config/task.conf
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@ -26,59 +26,58 @@ yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS] [BENCHMARKS]
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/io_tc1/rtl/*.v
#bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/unsigned_mult_80/rtl/*.v
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/bin2bcd/bin2bcd.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter/counter.v
#bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/rs_decoder/rtl/rs_decoder.v
#bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/simon_bit_serial/rtl/*.v
#bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sha256/rtl/*.v
#cavlc_top requires async reset/preset #cavlc_top requires async reset/preset
#bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cavlc_top/rtl/*.v
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/cf_fft_256_8/rtl/*.v
# counter120bitx5 requires 5 clocks # counter120bitx5 requires 5 clocks
#bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter120bitx5/rtl/*.v
#bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/counter_16bit/rtl/*.v
#bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/dct_mac/rtl/*.v
#bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/des_perf/rtl/*.v
#bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/diffeq_f_systemC/rtl/*.v
#i2c_master_top requires async reset/preset #i2c_master_top requires async reset/preset
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/i2c_master_top/rtl/*.v
#iir requires async reset/preset #iir requires async reset/preset
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/iir/rtl/*.v
#jpeg_qnr requires async reset/preset #jpeg_qnr requires async reset/preset
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/jpeg_qnr/rtl/*.v
#bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/multi_enc_decx2x4/rtl/*.v
# sdc_controller requires 4 clocks # sdc_controller requires 4 clocks
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/quicklogic_tests/sdc_controller/rtl/*.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench0_top = io_tc1 bench0_top = io_tc1
#bench1_top = unsigned_mult_80 bench1_top = unsigned_mult_80
#bench2_top = bin2bcd bench2_top = bin2bcd
bench3_top = counter bench3_top = counter
#bench5_top = rs_decoder_top bench5_top = rs_decoder_top
#bench6_top = top_module bench6_top = top_module
#bench7_top = sha256 bench7_top = sha256
#bench8_top = cavlc_top bench8_top = cavlc_top
#bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench8_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
#bench9_top = cf_fft_256_8 bench9_top = cf_fft_256_8
#bench10_top = counter120bitx5 bench10_top = counter120bitx5
#bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys bench10_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
#bench11_top = top bench11_top = top
#bench12_top = dct_mac bench12_top = dct_mac
#bench13_top = des_perf bench13_top = des_perf
#bench14_top = diffeq_f_systemC bench14_top = diffeq_f_systemC
#bench15_top = i2c_master_top #bench15_top = i2c_master_top
#bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys #bench15_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
#bench16_top = iir bench16_top = iir
#bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench16_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
#bench17_top = jpeg_qnr bench17_top = jpeg_qnr
#bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys bench17_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
#bench18_top = multi_enc_decx2x4 bench18_top = multi_enc_decx2x4
# sdc_controller requires 4 clocks
#bench19_top = sdc_controller #bench19_top = sdc_controller
#bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys #bench19_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys

2
yosys-plugins

@ -1 +1 @@
Subproject commit c44f188756783b2a9bc7197a0c72fd3f3698da1f Subproject commit e3204198bd50f14624d756b74f32c162dc5b0d0a