Added docuementation for fpga_flow
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Ganesh Gore
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02137805c7
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06c0dbb328
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@ -16,6 +16,9 @@ ALL_SPHINXOPTS = -d $(BUILDDIR)/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(SO
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help:
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@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
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livehtml:
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sphinx-autobuild -b html $(ALL_SPHINXOPTS) $(BUILDDIR)/html
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clean:
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rm -rf $(BUILDDIR)/*
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@ -0,0 +1,181 @@
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.. _run_fpga_flow:
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run_fpga_flow
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---------------
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This python script executes the supported openfpga flow for a
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single benchmark and architecture file for given script parameters.
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The script is located at::
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${OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py
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.. program:: run_fpga_flow.py
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Basic Usage
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~~~~~~~~~~~
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At a minimum ``open_fpga_flow.py`` requires following command-line arguments::
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open_fpga_flow.py <architecture_file> <benchmark_files> --top_module <top_module_name>
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where:
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* ``<architecture_file>`` is the target :ref:`FPGA architecture <fpga_architecture_description>`
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* ``<circuit_file>`` The list of files in the benchmark (Supports ../directory/\*.v)
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* ``<top_module_name>`` The name of the top level module in Verilog project
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.. note::
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The script will create a ``tmp`` run directory in base OpenFPGA path, unless otherwise specified with the :option:`--run_dir` option.
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All stages of the flow will be run within run directory.
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Several intermediate files will be generated and maintian in run directory.
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The path variables declared in architecture XML file will be resolved with absolute path and copied to the ``tmp/arch`` directory before executing flow.
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All the benchmark files provided will be copied to ``tmp/bench`` directory without maintaining any directory structure.
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**Users should ensure that no important files are kept in this directory as script will clear directory before each execution**
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OpenFPGA Variables
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~~~~~~~~~~~~~~~~~~
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Frequently, while running OpenFPGA flow User is suppose to refer external files.
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To avoid long names and referencing errors user can use
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following openfpga variables.
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These variables are resolved with absolute path while execution making
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each run independent of launch directory.
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* ``<OPENFPGA_PATH>`` Path to the base OpenFPGA directory
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* ``<OPENFPGA_FLOW_PATH>`` Path to the run_fpga_flow script directory
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* ``<SPICENETLIST_PATH>`` Path where spice netlists are saved
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* ``<VERILOG_PATH>`` Path where verilog modules are saved
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* ``<TECH_PATH>`` Path where all characterized XML files are stored
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For example in architecture file path vairable can be used as follows::
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.... lib_path="${TECH_PATH}/PTM_45nm/45nm.pm" ....
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Output
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~~~~~~
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Based on which flow is executed, resulting intermediate files are generated in run_directory
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The output log of the script provides status of each stage to the user.
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If any stage failed to execute, the output log will indicate the stage at which execution failed, and execution traceback.
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In case of successful execution, The openfpga flow script will parse
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parameters lited in configuration from different result files and will create
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``vpr_stat.txt``, ``vpr_stat_power.txt`` \(optional\) file in run_directory.
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Advanced Usage
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~~~~~~~~~~~~~~
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User can pass additional *optional* command arguments to ``run_fpga_flow.py`` script::
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run_fpga_flow.py <architecture_file> <benchmark_files> [<options>] [<vpr_options>] [<fpga-verilog_options>] [<fpga-spice_options>] [<fpga-bitstream_options>] [<ace_options>]
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where:
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* ``<options>`` are additional arguments passed to ``run_fpga_flow.py`` (described below),
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* ``<vpr_options>`` Any argument prefixed with ``--vpr-*`` will be forwarded to vpr script as it is. The detail of supported vpr argument is available ``Add corrrect reference``
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* ``<fpga-verilog_options>`` are any arguments not recognized by ``run_vtr_flow.pl``. These will be forwarded to VPR.
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* ``<ace_options>`` these arguments will be passed to ACE activity estimator program
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For example::
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run_fpga_flow.py my_circuit.v my_arch.xml -track_memory_usage --pack --place
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will run the VTR flow to map the circuit ``my_circuit.v`` onto the architecture ``my_arch.xml``; the arguments ``--pack`` and ``--place`` will be passed to VPR (since they are unrecognized arguments to ``run_vtr_flow.pl``).
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They will cause VPR to perform only :ref:`packing and placement <general_options>`.
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Detailed Command-line Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. Note:: All the commnadline arguments starting with ``vpr_*`` , ``fpga-verilog_*`` , ``fpga-spice_*`` or ``fpga-bitstream_*`` will be passed to VPR without suffix
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General Arguments
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^^^^^^^^^^^^^^^^^
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.. option:: --top_module <name>
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Provide top module name of the benchmark. Default ``top``
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.. option:: --run_dir <directory_path>
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Using this option user can provide custom path as a run directory. Default is ``tmp`` directory in OpenFPGA root path.
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.. option:: --K <lut_inputs>
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This option defines the number of inputs to the LUT. By default script parses provided architecture file and finds out inputs to the biggest LUT.
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.. option:: --yosys_tmpl <yosys_template_file>
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This option allows user to provide a custom yosys template
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while running a yosys_vpr flow. Default template is stored in a directory ``open_fpga_flow\misc\ys_tmpl_yosys_vpr_flow.ys``. Yosys template script supports ``TOP_MODULE`` ``READ_VERILOG_FILE`` ``LUT_SIZE`` & ``OUTPUT_BLIF`` variables, which can be used as ``${var_name}``. Alternately, user can create a copy and modify according to their need.
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.. option:: --debug
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To enable detail logs printing
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.. option:: --flow_config
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User can provide option flow ocnfiguration file to override some of the default script paramteres.
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for detail information refer :ref:`OpenFPGA Flow Configuration <OpenFPGA_Conf_File>`
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ACE Arguments
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^^^^^^^^^^^^^
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.. option:: --black_box_ace
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Performs ACE simulation on black box [deprecated]
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VPR RUN Arguments
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^^^^^^^^^^^^^^^^^
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.. option:: --fix_route_chan_width <channel_number>
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Perfoms VPR implementation for fixed number of channels defined as the 'channel_number'
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.. option:: --min_route_chan_width <percentage_slack>
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Performs VPR implementation to get minimum channel width and then perform fixed channel rerouting with ``percentage_slack`` increase in the channle width.
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.. option:: --max_route_width_retry <max_retry_count>
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Number of times the channel width should be incresese and attempt VPR implmenetation, while performaning ``min_route_chan_width``
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.. option:: --power
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.. option:: --power_tech
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blif_vpr_flow Arguments
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^^^^^^^^^^^^^^^^^^^^^^^^
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.. option:: --activity_file
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Activity to be used for the given benchmark while running ``blif_vpr_flow``
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.. option:: --base_verilog
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Verilog benchmark file to perform verification while running ``bliff_vpr_flow``
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.. _OpenFPGA_Conf_File:
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OpenFPGA Flow Configuration file
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The OpenFPGA Flow configuration file consists of following sections
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* ``CAD_TOOLS_PATH``
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Lists executable file path for different CAD tools used in the script
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* ``FLOW_SCRIPT_CONFIG``
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Lists the supported flows by the script.
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* ``DEFAULT_PARSE_RESULT_VPR``
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Default prarameters to parse from Place, Pack and Route output.
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* ``DEFAULT_PARSE_RESULT_POWER``
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Default prarameters to parse from VPR power analysis output.
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* ``INTERMIDIATE_FILE_PREFIX``
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[Not implemented yet]
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Default OpenFPGA_flow Configuration file is located in ``open_fpga_flow\misc\fpgaflow_default_tool_path.conf``.
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User supplied configuration file overrides or extendes the dafult configuration.
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@ -43,9 +43,15 @@ openfpga_base_dir = os.path.abspath(
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launch_dir = os.getcwd()
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# Path section to append in configuration file to interpolate path
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script_env_vars = {"PATH": {
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"OPENFPGA_FLOW_PATH": flow_script_dir,
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"OPENFPGA_PATH": openfpga_base_dir}}
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script_env_vars = ({"PATH": {
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"OPENFPGA_FLOW_PATH": task_script_dir,
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"ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
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"BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
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"TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
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"SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
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"VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
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"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
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os.pardir))}})
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Reading command-line argument
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@ -66,7 +72,7 @@ parser.add_argument('benchmark_files', type=str, nargs='+')
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# Optional arguments
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parser.add_argument('--top_module', type=str, default="top")
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parser.add_argument('--fpga_flow', type=str, default="yosys_vpr")
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parser.add_argument('--cad_tool_conf', type=str,
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parser.add_argument('--flow_config', type=str,
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help="CAD tools path overrides default setting")
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parser.add_argument('--run_dir', type=str,
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default=os.path.join(openfpga_base_dir, 'tmp'),
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@ -281,8 +287,8 @@ def read_script_config():
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default_cad_tool_conf = os.path.join(flow_script_dir, os.pardir, 'misc',
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'fpgaflow_default_tool_path.conf')
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config.read_file(open(default_cad_tool_conf))
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if args.cad_tool_conf:
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config.read_file(open(args.cad_tool_conf))
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if args.flow_config:
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config.read_file(open(args.flow_config))
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if not "CAD_TOOLS_PATH" in config.sections():
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clean_up_and_exit("Missing CAD_TOOLS_PATH in openfpga_flow config")
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cad_tools = config["CAD_TOOLS_PATH"]
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