From 06b018cfe7f15b3200ece0d653abf5c2c4f22f89 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 3 Oct 2021 16:05:33 -0700 Subject: [PATCH] [FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature --- openfpga/src/utils/fabric_bitstream_utils.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp index 31163efcc..cc14dfe84 100644 --- a/openfpga/src/utils/fabric_bitstream_utils.cpp +++ b/openfpga/src/utils/fabric_bitstream_utils.cpp @@ -410,7 +410,7 @@ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_b std::vector reshaped_bl_vectors = reshape_bitstream_vectors_to_first_element(bl_vec, '0'); /* Reverse the vectors due to the shift register chain nature: first-in first-out */ - //std::reverse(reshaped_bl_vectors.begin(), reshaped_bl_vectors.end()); + std::reverse(reshaped_bl_vectors.begin(), reshaped_bl_vectors.end()); /* Add the BL word to final bitstream */ for (const auto& reshaped_bl_vec : reshaped_bl_vectors) { fabric_bits.add_bl_vectors(word_id, reshaped_bl_vec); @@ -418,7 +418,7 @@ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_b std::vector reshaped_wl_vectors = reshape_bitstream_vectors_to_first_element(wl_vec, '0'); /* Reverse the vectors due to the shift register chain nature: first-in first-out */ - //std::reverse(reshaped_wl_vectors.begin(), reshaped_wl_vectors.end()); + std::reverse(reshaped_wl_vectors.begin(), reshaped_wl_vectors.end()); /* Add the BL word to final bitstream */ for (const auto& reshaped_wl_vec : reshaped_wl_vectors) { fabric_bits.add_wl_vectors(word_id, reshaped_wl_vec);