From 068d9943e746c4d830d9d6c6e709f073512f6d87 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jun 2020 11:41:36 -0600 Subject: [PATCH] update all the templates and regression test cases with simulation settings --- .../duplicated_grid_pin_example_script.openfpga | 2 +- openfpga_flow/OpenFPGAShellScripts/example_script.openfpga | 2 +- .../fast_configuration_example_script.openfpga | 2 +- .../flatten_routing_example_script.openfpga | 2 +- .../OpenFPGAShellScripts/full_testbench_example_script.openfpga | 2 +- .../generate_fabric_example_script.openfpga | 2 +- .../generate_testbench_example_script.openfpga | 2 +- .../implicit_verilog_example_script.openfpga | 2 +- openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga | 2 +- .../OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga | 2 +- .../tasks/openfpga_shell/behavioral_verilog/config/task.conf | 1 + .../tasks/openfpga_shell/bram/dpram16k/config/task.conf | 1 + .../tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf | 2 +- .../tasks/openfpga_shell/duplicated_grid_pin/config/task.conf | 1 + .../openfpga_shell/fabric_chain/adder_chain/config/task.conf | 1 + .../openfpga_shell/fabric_chain/register_chain/config/task.conf | 1 + .../openfpga_shell/fabric_chain/scan_chain/config/task.conf | 1 + .../openfpga_shell/fixed_simulation_settings/config/task.conf | 1 + .../tasks/openfpga_shell/flatten_routing/config/task.conf | 1 + .../full_testbench/configuration_frame/config/task.conf | 1 + .../full_testbench/fast_configuration_frame/config/task.conf | 1 + .../full_testbench/fast_memory_bank/config/task.conf | 1 + .../full_testbench/flatten_memory/config/task.conf | 1 + .../openfpga_shell/full_testbench/memory_bank/config/task.conf | 1 + .../tasks/openfpga_shell/generate_fabric/config/task.conf | 1 + .../tasks/openfpga_shell/generate_testbench/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf | 1 + .../tasks/openfpga_shell/implicit_verilog/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf | 1 + .../tasks/openfpga_shell/io/multi_io_capacity/config/task.conf | 1 + .../tasks/openfpga_shell/io/reduced_io/config/task.conf | 1 + .../tasks/openfpga_shell/lut_design/frac_lut/config/task.conf | 1 + .../lut_design/intermediate_buffer/config/task.conf | 1 + .../openfpga_shell/lut_design/single_mode/config/task.conf | 1 + .../openfpga_shell/mux_design/local_encoder/config/task.conf | 1 + .../openfpga_shell/mux_design/stdcell_mux2/config/task.conf | 1 + .../openfpga_shell/mux_design/tree_structure/config/task.conf | 1 + .../preconfig_testbench/configuration_chain/config/task.conf | 1 + .../preconfig_testbench/configuration_frame/config/task.conf | 1 + .../preconfig_testbench/flatten_memory/config/task.conf | 1 + .../preconfig_testbench/memory_bank/config/task.conf | 1 + .../tasks/openfpga_shell/sdc_time_unit/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf | 1 + openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf | 1 + 44 files changed, 44 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga index 83707cf53..ae729290e 100644 --- a/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/duplicated_grid_pin_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga index 83707cf53..ae729290e 100644 --- a/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga index 56d05257c..fceabcaaa 100644 --- a/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index fa376dbe3..5ab1c56b6 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga index 83707cf53..ae729290e 100644 --- a/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga index 434c573e1..38ebc9d28 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_fabric_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga index 6fe802168..971f8d374 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_testbench_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga index 021488557..e86ba055e 100644 --- a/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/implicit_verilog_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga index ebd6c217c..dc7af60ae 100644 --- a/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffe read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga index 3411f6e87..36c3c88b9 100644 --- a/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/sdc_time_unit_example_script.openfpga @@ -6,7 +6,7 @@ vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} # Read OpenFPGA simulation settings -#read_openfpga_simulation_setting -f OPENFPGA_SIM_SETTING_FILE +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options diff --git a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf index e11da844f..3693bd3db 100644 --- a/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/behavioral_verilog/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf index 4996f42e2..93e491745 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf index 5cfc3ce57..3d89335d9 100644 --- a/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/bram/wide_dpram16k/config/task.conf @@ -16,7 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf index f2777f7ee..328203c08 100644 --- a/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/duplicated_grid_pin/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf index 5e9533e36..4ab0447a3 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/adder_chain/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf index 1b76cb3e9..06441b7f3 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/register_chain/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf index ac398aa4c..0d1f49c94 100644 --- a/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fabric_chain/scan_chain/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf index 4875931e3..813aabc03 100644 --- a/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/fixed_simulation_settings/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf index 2879e95ed..36bdb28bd 100644 --- a/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/flatten_routing/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf index 2f5baca4d..e99b9c2ab 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/configuration_frame/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf index 55c98dda1..0a95022d3 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_configuration_frame/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf index 61b3d8b72..eb3aafbd3 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/fast_memory_bank/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf index d2bf1bb9f..b893a163f 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/flatten_memory/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf index b000c0ba6..fadc53968 100644 --- a/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/full_testbench/memory_bank/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf index 75bc6c703..077bafbc5 100644 --- a/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/generate_fabric/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf index 9540b767f..02d4fb597 100644 --- a/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/generate_testbench/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf index c0198598e..2d8c162d0 100644 --- a/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/hard_adder/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf index 4040caee1..36cc8208d 100644 --- a/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/implicit_verilog/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf index 0f4727657..ab8b7849e 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/aib/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml ##################################### # Debugging status diff --git a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf index 8ae3286c5..c751ed64c 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/multi_io_capacity/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf index 190acfda7..17b2c8564 100644 --- a/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/io/reduced_io/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf index 030c0d41e..39bbeb784 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/frac_lut/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf index b2535bd7c..885569b51 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/intermediate_buffer/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf index 4216a7482..0c735e07f 100644 --- a/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/lut_design/single_mode/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf index 76cf4b589..7b48cf6e2 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/local_encoder/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf index 60df151e7..08bebdf04 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/stdcell_mux2/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf index 3f8b56582..48633266c 100644 --- a/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/mux_design/tree_structure/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf index 3fd340a7b..9c9fc9627 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_chain/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf index 4a41fc671..e55a6ea8e 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/configuration_frame/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf index 1a02eb45f..78d1e818c 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/flatten_memory/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf index 75579406c..c9505c1d5 100644 --- a/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/preconfig_testbench/memory_bank/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf index 332020fab..11cd98766 100644 --- a/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/sdc_time_unit/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf index b42e17287..d7d55eb62 100644 --- a/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/spypad/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml diff --git a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf index 7dcf88915..a7e1939ed 100644 --- a/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf +++ b/openfpga_flow/tasks/openfpga_shell/untileable/config/task.conf @@ -16,6 +16,7 @@ verilog_output=true timeout_each_job = 20*60 fpga_flow=vpr_blif openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_40nm.xml