From 05f08c2f2510bb1378dc8cf3350538aa24d6ae8d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 26 Apr 2021 12:05:37 -0600
Subject: [PATCH] Update PULL_REQUEST_TEMPLATE.md

---
 .github/PULL_REQUEST_TEMPLATE.md | 64 +++++++++++++++++---------------
 1 file changed, 35 insertions(+), 29 deletions(-)

diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md
index d1c458c04..f1b1063fd 100644
--- a/.github/PULL_REQUEST_TEMPLATE.md
+++ b/.github/PULL_REQUEST_TEMPLATE.md
@@ -1,33 +1,39 @@
----
-name: Pull request
-about: Push a change to this project
----
+> ### Motivate of the pull request
+> - [ ] To address an existing issue. If so, please provide a link to the issue: <issue id>
+> - [ ] Breaking new feature. If so, please describe details in the description part.
 
-### Motivate of the pull request
-- [ ] To address an existing issue. If so, please provide a link to the issue.
-- [ ] Breaking new feature. If so, please decribe details in the description part.
+> ### Describe the technical details
+> #### What is currently done? (Provide issue link if applicable)
+> <!-- Please provide a list of limitations if not specified in any issue -->
+> <!-- Below is a template, uncomment upon your needs -->
+> <!-- Currently, OpenFPGA has the following limitations: -->
+> <!-- - [ ] technical details about limitation  -->
+> <!-- - [ ] more limitations  -->
+>
+> #### What does this pull request change?
+> <!-- Please provide a list of highlights of your changes. -->
+> <!-- Below is a template, uncomment upon your needs -->
+> <!-- This PR improves in the following aspects: -->
+> <!-- - [ ] details about the technical highlight -->
+> <!-- - [ ] <more technical highlights -->
 
-### Describe the technical details
-- What is currently done? (Provide issue link if applicable)
-- What does this pull request change?
+> ### Which part of the code base require a change
+> <!-- In general, modification on existing submodules are not acceptable. You should push changes to upstream. -->
+> - [ ] VPR
+> - [ ] Tileable routing architecture generator
+> - [ ] OpenFPGA libraries
+> - [ ] FPGA-Verilog
+> - [ ] FPGA-Bitstream
+> - [ ] FPGA-SDC
+> - [ ] FPGA-SPICE
+> - [ ] Flow scripts
+> - [ ] Architecture library
+> - [ ] Cell library
+> - [ ] Documentation
+> - [ ] Regression tests
+> - [ ] Continous Integration (CI) scripts
 
-### Which part of the code base require a change
-**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
-- [ ] VPR
-- [ ] OpenFPGA libraries
-- [ ] FPGA-Verilog
-- [ ] FPGA-Bitstream
-- [ ] FPGA-SDC
-- [ ] FPGA-SPICE
-- [ ] Flow scripts
-- [ ] Architecture library
-- [ ] Cell library
+> ### Impact of the pull request
 
-### Checklist of the pull request
-- [ ] Require code changes. 
-- [ ] Require new tests to be added
-- [ ] Require an update on documentation
-
-### Impact of the pull request
-- [ ] Require a change on Quality of Results (QoR)
-- [ ] Break back-compatibility. If so, please list who may be influenced.
+> - [ ] Require a change on Quality of Results (QoR)
+> - [ ] Break back-compatibility. If so, please list who may be influenced.