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[core] code format

This commit is contained in:
tangxifan 2023-09-16 18:24:38 -07:00
parent 6fc2924438
commit 058bb1ef51
5 changed files with 56 additions and 63 deletions
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17
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -61,8 +61,7 @@ int fpga_fabric_verilog(
const DecoderLibrary &decoder_lib, const DeviceContext &device_ctx, const DecoderLibrary &decoder_lib, const DeviceContext &device_ctx,
const VprDeviceAnnotation &device_annotation, const VprDeviceAnnotation &device_annotation,
const DeviceRRGSB &device_rr_gsb, const FabricTile &fabric_tile, const DeviceRRGSB &device_rr_gsb, const FabricTile &fabric_tile,
const ModuleNameMap& module_name_map, const ModuleNameMap &module_name_map, const FabricVerilogOption &options) {
const FabricVerilogOption &options) {
vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n"); vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
int status_code = CMD_EXEC_SUCCESS; int status_code = CMD_EXEC_SUCCESS;
@ -112,13 +111,14 @@ int fpga_fabric_verilog(
/* Generate routing blocks */ /* Generate routing blocks */
if (true == options.compress_routing()) { if (true == options.compress_routing()) {
print_verilog_unique_routing_modules( print_verilog_unique_routing_modules(
netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map, netlist_manager, const_cast<const ModuleManager &>(module_manager),
device_rr_gsb, rr_dir_path, std::string(DEFAULT_RR_DIR_NAME), options); module_name_map, device_rr_gsb, rr_dir_path,
std::string(DEFAULT_RR_DIR_NAME), options);
} else { } else {
VTR_ASSERT(false == options.compress_routing()); VTR_ASSERT(false == options.compress_routing());
print_verilog_flatten_routing_modules( print_verilog_flatten_routing_modules(
netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map, netlist_manager, const_cast<const ModuleManager &>(module_manager),
device_rr_gsb, device_ctx.rr_graph, rr_dir_path, module_name_map, device_rr_gsb, device_ctx.rr_graph, rr_dir_path,
std::string(DEFAULT_RR_DIR_NAME), options); std::string(DEFAULT_RR_DIR_NAME), options);
} }
@ -131,8 +131,9 @@ int fpga_fabric_verilog(
/* Generate tiles */ /* Generate tiles */
if (!fabric_tile.empty()) { if (!fabric_tile.empty()) {
status_code = print_verilog_tiles( status_code = print_verilog_tiles(
netlist_manager, const_cast<const ModuleManager &>(module_manager), module_name_map, netlist_manager, const_cast<const ModuleManager &>(module_manager),
tile_dir_path, fabric_tile, std::string(DEFAULT_TILE_DIR_NAME), options); module_name_map, tile_dir_path, fabric_tile,
std::string(DEFAULT_TILE_DIR_NAME), options);
if (status_code != CMD_EXEC_SUCCESS) { if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }

5
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -20,9 +20,9 @@
#include "fabric_verilog_options.h" #include "fabric_verilog_options.h"
#include "io_location_map.h" #include "io_location_map.h"
#include "io_name_map.h" #include "io_name_map.h"
#include "module_name_map.h"
#include "memory_bank_shift_register_banks.h" #include "memory_bank_shift_register_banks.h"
#include "module_manager.h" #include "module_manager.h"
#include "module_name_map.h"
#include "mux_library.h" #include "mux_library.h"
#include "netlist_manager.h" #include "netlist_manager.h"
#include "pin_constraints.h" #include "pin_constraints.h"
@ -46,8 +46,7 @@ int fpga_fabric_verilog(
const DecoderLibrary& decoder_lib, const DeviceContext& device_ctx, const DecoderLibrary& decoder_lib, const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation, const VprDeviceAnnotation& device_annotation,
const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const FabricVerilogOption& options);
const FabricVerilogOption& options);
int fpga_verilog_full_testbench( int fpga_verilog_full_testbench(
const ModuleManager& module_manager, const ModuleManager& module_manager,

70
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -77,10 +77,9 @@ namespace openfpga {
********************************************************************/ ********************************************************************/
static void print_verilog_routing_connection_box_unique_module( static void print_verilog_routing_connection_box_unique_module(
NetlistManager& netlist_manager, const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const std::string& subckt_dir,
const std::string& subckt_dir, const std::string& subckt_dir_name, const std::string& subckt_dir_name, const RRGSB& rr_gsb,
const RRGSB& rr_gsb, const t_rr_type& cb_type, const t_rr_type& cb_type, const FabricVerilogOption& options) {
const FabricVerilogOption& options) {
/* Create the netlist */ /* Create the netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type),
rr_gsb.get_cb_y(cb_type)); rr_gsb.get_cb_y(cb_type));
@ -103,7 +102,8 @@ static void print_verilog_routing_connection_box_unique_module(
/* Create a Verilog Module based on the circuit model, and add to module /* Create a Verilog Module based on the circuit model, and add to module
* manager */ * manager */
std::string cb_module_name = module_name_map.name(generate_connection_block_module_name(cb_type, gsb_coordinate)); std::string cb_module_name = module_name_map.name(
generate_connection_block_module_name(cb_type, gsb_coordinate));
ModuleId cb_module = module_manager.find_module(cb_module_name); ModuleId cb_module = module_manager.find_module(cb_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
@ -192,9 +192,9 @@ static void print_verilog_routing_connection_box_unique_module(
********************************************************************/ ********************************************************************/
static void print_verilog_routing_switch_box_unique_module( static void print_verilog_routing_switch_box_unique_module(
NetlistManager& netlist_manager, const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const std::string& subckt_dir,
const std::string& subckt_dir, const std::string& subckt_dir_name, const std::string& subckt_dir_name, const RRGSB& rr_gsb,
const RRGSB& rr_gsb, const FabricVerilogOption& options) { const FabricVerilogOption& options) {
/* Create the netlist */ /* Create the netlist */
vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
std::string verilog_fname(generate_routing_block_netlist_name( std::string verilog_fname(generate_routing_block_netlist_name(
@ -217,9 +217,9 @@ static void print_verilog_routing_switch_box_unique_module(
/* Create a Verilog Module based on the circuit model, and add to module /* Create a Verilog Module based on the circuit model, and add to module
* manager */ * manager */
std::string sb_module_name = module_name_map.name(generate_switch_block_module_name(gsb_coordinate)); std::string sb_module_name =
ModuleId sb_module = module_manager.find_module( module_name_map.name(generate_switch_block_module_name(gsb_coordinate));
sb_module_name); ModuleId sb_module = module_manager.find_module(sb_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
/* Write the verilog module */ /* Write the verilog module */
@ -248,10 +248,9 @@ static void print_verilog_routing_switch_box_unique_module(
*******************************************************************/ *******************************************************************/
static void print_verilog_flatten_connection_block_modules( static void print_verilog_flatten_connection_block_modules(
NetlistManager& netlist_manager, const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
const DeviceRRGSB& device_rr_gsb, const std::string& subckt_dir, const std::string& subckt_dir, const std::string& subckt_dir_name,
const std::string& subckt_dir_name, const t_rr_type& cb_type, const t_rr_type& cb_type, const FabricVerilogOption& options) {
const FabricVerilogOption& options) {
/* Build unique X-direction connection block modules */ /* Build unique X-direction connection block modules */
vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range(); vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
@ -266,8 +265,8 @@ static void print_verilog_flatten_connection_block_modules(
continue; continue;
} }
print_verilog_routing_connection_box_unique_module( print_verilog_routing_connection_box_unique_module(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, rr_gsb, netlist_manager, module_manager, module_name_map, subckt_dir,
cb_type, options); subckt_dir_name, rr_gsb, cb_type, options);
} }
} }
} }
@ -281,14 +280,11 @@ static void print_verilog_flatten_connection_block_modules(
* 1. Connection blocks * 1. Connection blocks
* 2. Switch blocks * 2. Switch blocks
*******************************************************************/ *******************************************************************/
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, void print_verilog_flatten_routing_modules(
const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const std::string& subckt_dir,
const RRGraphView& rr_graph, const std::string& subckt_dir_name, const FabricVerilogOption& options) {
const std::string& subckt_dir,
const std::string& subckt_dir_name,
const FabricVerilogOption& options) {
/* Create a vector to contain all the Verilog netlist names that have been /* Create a vector to contain all the Verilog netlist names that have been
* generated in this function */ * generated in this function */
std::vector<std::string> netlist_names; std::vector<std::string> netlist_names;
@ -303,18 +299,18 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
continue; continue;
} }
print_verilog_routing_switch_box_unique_module( print_verilog_routing_switch_box_unique_module(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, rr_gsb, netlist_manager, module_manager, module_name_map, subckt_dir,
options); subckt_dir_name, rr_gsb, options);
} }
} }
print_verilog_flatten_connection_block_modules( print_verilog_flatten_connection_block_modules(
netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir, subckt_dir_name, netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir,
CHANX, options); subckt_dir_name, CHANX, options);
print_verilog_flatten_connection_block_modules( print_verilog_flatten_connection_block_modules(
netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir, subckt_dir_name, netlist_manager, module_manager, module_name_map, device_rr_gsb, subckt_dir,
CHANY, options); subckt_dir_name, CHANY, options);
} }
/******************************************************************** /********************************************************************
@ -342,8 +338,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
print_verilog_routing_switch_box_unique_module( print_verilog_routing_switch_box_unique_module(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, netlist_manager, module_manager, module_name_map, subckt_dir,
unique_mirror, options); subckt_dir_name, unique_mirror, options);
} }
/* Build unique X-direction connection block modules */ /* Build unique X-direction connection block modules */
@ -352,8 +348,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
print_verilog_routing_connection_box_unique_module( print_verilog_routing_connection_box_unique_module(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, netlist_manager, module_manager, module_name_map, subckt_dir,
unique_mirror, CHANX, options); subckt_dir_name, unique_mirror, CHANX, options);
} }
/* Build unique X-direction connection block modules */ /* Build unique X-direction connection block modules */
@ -362,8 +358,8 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
print_verilog_routing_connection_box_unique_module( print_verilog_routing_connection_box_unique_module(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name, netlist_manager, module_manager, module_name_map, subckt_dir,
unique_mirror, CHANY, options); subckt_dir_name, unique_mirror, CHANY, options);
} }
VTR_LOG("\n"); VTR_LOG("\n");

13
openfpga/src/fpga_verilog/verilog_routing.h
View File

@ -20,14 +20,11 @@
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, void print_verilog_flatten_routing_modules(
const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const DeviceRRGSB& device_rr_gsb,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const std::string& subckt_dir,
const RRGraphView& rr_graph, const std::string& subckt_dir_name, const FabricVerilogOption& options);
const std::string& subckt_dir,
const std::string& subckt_dir_name,
const FabricVerilogOption& options);
void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager, const ModuleManager& module_manager,

14
openfpga/src/fpga_verilog/verilog_tile.cpp
View File

@ -26,14 +26,14 @@ namespace openfpga {
*******************************************************************/ *******************************************************************/
static int print_verilog_tile_module_netlist( static int print_verilog_tile_module_netlist(
NetlistManager& netlist_manager, const ModuleManager& module_manager, NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map, const ModuleNameMap& module_name_map, const std::string& verilog_dir,
const std::string& verilog_dir, const FabricTile& fabric_tile, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
const FabricTileId& fabric_tile_id, const std::string& subckt_dir_name, const std::string& subckt_dir_name, const FabricVerilogOption& options) {
const FabricVerilogOption& options) {
/* Create a module as the top-level fabric, and add it to the module manager /* Create a module as the top-level fabric, and add it to the module manager
*/ */
vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id); vtr::Point<size_t> tile_coord = fabric_tile.tile_coordinate(fabric_tile_id);
std::string tile_module_name = module_name_map.name(generate_tile_module_name(tile_coord)); std::string tile_module_name =
module_name_map.name(generate_tile_module_name(tile_coord));
ModuleId tile_module = module_manager.find_module(tile_module_name); ModuleId tile_module = module_manager.find_module(tile_module_name);
if (!module_manager.valid_module_id(tile_module)) { if (!module_manager.valid_module_id(tile_module)) {
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
@ -102,8 +102,8 @@ int print_verilog_tiles(NetlistManager& netlist_manager,
/* Build a module for each unique tile */ /* Build a module for each unique tile */
for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) { for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
status_code = print_verilog_tile_module_netlist( status_code = print_verilog_tile_module_netlist(
netlist_manager, module_manager, module_name_map, verilog_dir, fabric_tile, fabric_tile_id, netlist_manager, module_manager, module_name_map, verilog_dir,
subckt_dir_name, options); fabric_tile, fabric_tile_id, subckt_dir_name, options);
if (status_code != CMD_EXEC_SUCCESS) { if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR; return CMD_EXEC_FATAL_ERROR;
} }