From 0450d57d82f09d7ee0603bf24b5913185d5f79e9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 20 Sep 2021 16:05:01 -0700
Subject: [PATCH] [Arch] Fixed critical bugs in the OpenFPGA architecture file
 for QL memory bank with WLR

---
 .../openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml
index 228f450a4..62f449b25 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbank_wlr_openfpga.xml
@@ -161,13 +161,13 @@
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
-      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAM" default_val="1"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAM_RE" default_val="1"/>
       <port type="input" prefix="outpad" lib_name="A" size="1"/>
       <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="ql_memory_bank" circuit_model_name="SRAM"/>
+    <organization type="ql_memory_bank" circuit_model_name="SRAM_RE"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>