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[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back

This commit is contained in:
tangxifan 2022-10-21 20:26:56 -07:00
parent 57b86eaebf
commit 04286508c8
1 changed files with 5 additions and 9 deletions
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14
openfpga_flow/tasks/benchmark_sweep/iwls2005/config/task.conf
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@ -39,20 +39,18 @@ bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/simple_spi/rtl/*.
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/tv80/rtl/*.v
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/vga_lcd/rtl/*.v
# AES core has two top modules that can be tested: encryption and decryption # AES core has two top modules that can be tested: encryption and decryption
# Synthesis is too long; skip it
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/aes_core/rtl/*.v
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v # FIXME: Yosys 0.22 has issues: ABC got stuck due to a lot of combinational loops. Bring this back when there is a new version
#bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/fpu/rtl/*.v
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/pci/rtl/*.v
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/spi/rtl/*.v
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/systemcaes/rtl/*.v
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/usb_funct/rtl/*.v
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/wb_conmax/rtl/*.v
## DES has two versions: area-optimized and performance optimized ## DES has two versions: area-optimized and performance optimized
# The DES has same top-level module name as systemcdes bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
# Currently openfpga flow has a bug which does not allow same top-level module name bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
#bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/area_opt/rtl/*.v
#bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/des/perf_opt/rtl/*.v
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/i2c/rtl/*.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/sasc/rtl/*.v
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/iwls2005/ss_pcm/rtl/*.v
@ -85,13 +83,11 @@ bench11_top = spi_top
bench12_top = aes bench12_top = aes
bench13_top = usbf_top bench13_top = usbf_top
bench14_top = wb_conmax_top bench14_top = wb_conmax_top
# Not sure either des or des3 is the top module. Need further investigation
bench15_top = des bench15_top = des
bench16_top = des3 bench16_top = des
bench17_top = i2c_master_top bench17_top = i2c_master_top
bench18_top = sasc_top bench18_top = sasc_top
bench19_top = pcm_slv_top bench19_top = pcm_slv_top
# May conflict with the top module name with other 'des' benchmark; This is a bug of openfpga flow scripts
bench20_top = des bench20_top = des
bench21_top = usb_phy bench21_top = usb_phy
bench22_top = wb_dma_top bench22_top = wb_dma_top