riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1736 from lnis-uofu/xt_clkntwk2 

[doc] typo
This commit is contained in:
tangxifan 2024-07-02 21:10:26 -07:00 committed by GitHub
parent 37c640faef abef0e3478
commit 0426d47026
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/source/manual/file_formats/clock_network.rst
View File

@ -39,7 +39,7 @@ Using the clock network description language, users can define multiple clock ne
.. _fig_prog_clock_network_example_2x2: .. _fig_prog_clock_network_example_2x2:
.. figure:: figures/prog_clock_network_example_2x2.png .. figure:: figures/prog_clk_network_example_2x2.png
:width: 100% :width: 100%
:alt: An example of programmable clock network considering a 2x2 FPGA fabric :alt: An example of programmable clock network considering a 2x2 FPGA fabric