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/********************************************************************
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* This file includes functions to generate Verilog submodules for LUTs
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********************************************************************/
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#include <string>
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#include <algorithm>
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#include "util.h"
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#include "vtr_assert.h"
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/* Device-level header files */
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#include "mux_graph.h"
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#include "module_manager.h"
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#include "physical_types.h"
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#include "vpr_types.h"
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#include "mux_utils.h"
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/* FPGA-X2P context header files */
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#include "spice_types.h"
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#include "fpga_x2p_naming.h"
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#include "fpga_x2p_utils.h"
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/* FPGA-Verilog context header files */
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#include "verilog_global.h"
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#include "verilog_writer_utils.h"
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#include "verilog_submodule_utils.h"
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#include "verilog_lut.h"
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/********************************************************************
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* Print a Verilog module for a LUT circuit model
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* This function supports both single-output and fracturable LUTs
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* The Verilog module will be organized in structural Verilog codes.
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* It will instanciate:
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* 1. Multiplexer used inside LUT
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* 2. Input buffers
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* 3. Input inverters
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* 4. Output buffers.
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* 6. AND/OR gates to tri-state LUT inputs
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********************************************************************/
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static
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void print_verilog_submodule_lut(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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std::fstream& fp,
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const CircuitModelId& circuit_model) {
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/* Ensure a valid file handler*/
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check_file_handler(fp);
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/* Get the global ports required by MUX (and any submodules) */
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std::vector<CircuitPortId> lut_global_ports = circuit_lib.model_global_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
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/* Get the input ports from the mux */
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std::vector<CircuitPortId> lut_input_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_INPUT, true);
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/* Get the output ports from the mux */
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std::vector<CircuitPortId> lut_output_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
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/* Classify SRAM ports into two categories: regular (not for mode select) and mode-select */
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std::vector<CircuitPortId> lut_regular_sram_ports;
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std::vector<CircuitPortId> lut_mode_select_sram_ports;
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{ /* Create a code block to keep some variables in local */
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/* Get the sram ports from the mux */
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std::vector<CircuitPortId> lut_sram_ports = circuit_lib.model_ports_by_type(circuit_model, SPICE_MODEL_PORT_SRAM, true);
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for (const auto& port : lut_sram_ports) {
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/* Bypass mode_select ports */
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if (true == circuit_lib.port_is_mode_select(port)) {
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lut_mode_select_sram_ports.push_back(port);
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continue;
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}
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VTR_ASSERT_SAFE (false == circuit_lib.port_is_mode_select(port));
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lut_regular_sram_ports.push_back(port);
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}
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}
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/* Make sure that the number of ports and sizes of ports are what we want */
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if (false == circuit_lib.is_lut_fracturable(circuit_model)) {
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/* Single-output LUTs:
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* We should have only 1 input port, 1 output port and 1 SRAM port
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*/
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VTR_ASSERT (1 == lut_input_ports.size());
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VTR_ASSERT (1 == lut_output_ports.size());
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VTR_ASSERT (1 == lut_regular_sram_ports.size());
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VTR_ASSERT (0 == lut_mode_select_sram_ports.size());
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} else {
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VTR_ASSERT (true == circuit_lib.is_lut_fracturable(circuit_model));
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/* Fracturable LUT:
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* We should have only 1 input port, a few output ports (fracturable outputs)
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* and two SRAM ports
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*/
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VTR_ASSERT (1 == lut_input_ports.size());
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VTR_ASSERT (1 <= lut_output_ports.size());
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VTR_ASSERT (1 == lut_regular_sram_ports.size());
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VTR_ASSERT (1 == lut_mode_select_sram_ports.size());
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}
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/* Create a Verilog Module based on the circuit model, and add to module manager */
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ModuleId module_id = module_manager.add_module(circuit_lib.model_name(circuit_model));
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VTR_ASSERT(ModuleId::INVALID() != module_id);
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/* Add module ports */
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/* Add each global port */
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for (const auto& port : lut_global_ports) {
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/* Configure each global port */
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BasicPort global_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, global_port, ModuleManager::MODULE_GLOBAL_PORT);
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}
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/* Add each input port */
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for (const auto& port : lut_input_ports) {
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BasicPort input_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, input_port, ModuleManager::MODULE_INPUT_PORT);
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}
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/* Add each output port */
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for (const auto& port : lut_output_ports) {
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BasicPort output_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, output_port, ModuleManager::MODULE_OUTPUT_PORT);
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}
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/* Add each regular (not mode select) SRAM port */
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for (const auto& port : lut_regular_sram_ports) {
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BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT);
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BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port));
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module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
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}
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/* Add each mode-select SRAM port */
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for (const auto& port : lut_mode_select_sram_ports) {
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BasicPort mem_port(circuit_lib.port_lib_name(port), circuit_lib.port_size(port));
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module_manager.add_port(module_id, mem_port, ModuleManager::MODULE_INPUT_PORT);
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BasicPort mem_inv_port(std::string(circuit_lib.port_lib_name(port) + "_inv"), circuit_lib.port_size(port));
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module_manager.add_port(module_id, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
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}
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/* dump module definition + ports */
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print_verilog_module_declaration(fp, module_manager, module_id);
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/* Print local wires for mode selector */
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/* Local wires for the output of mode selector */
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BasicPort mode_select_output_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_mode"), circuit_lib.port_size(lut_input_ports[0]));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, mode_select_output_port) << ";" << std::endl;
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/* Local wires for the output of input inverters */
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BasicPort inverted_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_b"), circuit_lib.port_size(lut_input_ports[0]));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, inverted_input_port) << ";" << std::endl;
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/* Local wires for the output of input buffers */
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BasicPort buffered_input_port(std::string(circuit_lib.port_lib_name(lut_input_ports[0]) + "_buf"), circuit_lib.port_size(lut_input_ports[0]));
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fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, buffered_input_port) << ";" << std::endl;
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/* Instanciate mode selecting circuit: AND/OR gate
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* By following the tri-state map of LUT input port
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* The wiring of input ports will be organized as follows
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*
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* LUT input
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* |
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* v
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* +----------+
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* | mode |
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* | selector |
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* +----------+
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* | mode_select_output_port
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* +-----------------+------------+
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* | |
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* +----------+ +---------+
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* | Inverter | | Buffer |
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* +----------+ +---------+
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* | inverter_input_port | buffered_input_port
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* v v
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* +--------------------------------------+
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* | LUT Multiplexing Structure |
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* +--------------------------------------+
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*/
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of model-select gates -----"));
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/* Get the tri-state port map for the input ports*/
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std::string tri_state_map = circuit_lib.port_tri_state_map(lut_input_ports[0]);
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size_t mode_select_port_lsb = 0;
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for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) {
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BasicPort cur_mode_select_output_port(mode_select_output_port.get_name(), pin, pin);
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BasicPort cur_input_port(circuit_lib.port_lib_name(lut_input_ports[0]), pin, pin);
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/* For an empty tri-state map or a '-' sign in tri-state map, we can short-wire mode select_output_ports */
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if (tri_state_map.empty() || ('-' == tri_state_map[pin]) ) {
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print_verilog_wire_connection(fp, cur_mode_select_output_port, cur_input_port, false);
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continue; /* Finish here */
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}
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/* Reach here, it means that we need a circuit for mode selection */
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BasicPort cur_lut_mode_select_sram_port(circuit_lib.port_lib_name(lut_mode_select_sram_ports[0]), mode_select_port_lsb, mode_select_port_lsb);
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enum e_spice_model_gate_type required_gate_type;
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if ('0' == tri_state_map[pin]) {
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/* We need a 2-input AND gate, in order to tri-state the input
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* Detailed circuit is as follow:
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* +---------+
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* SRAM --->| 2-input |----> mode_select_output_port
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* LUT input--->| AND |
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* +---------+
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* When SRAM is set to logic 0, the LUT input is tri-stated
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* When SRAM is set to logic 1, the LUT input is effective to the downstream circuits
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*/
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required_gate_type = SPICE_MODEL_GATE_AND;
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} else {
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VTR_ASSERT ('1' == tri_state_map[pin]);
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/* We need a 2-input OR gate, in order to tri-state the input
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* Detailed circuit is as follow:
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* +---------+
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* SRAM --->| 2-input |----> mode_select_output_port
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* LUT input--->| OR |
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* +---------+
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* When SRAM is set to logic 1, the LUT input is tri-stated
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* When SRAM is set to logic 0, the LUT input is effective to the downstream circuits
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*/
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required_gate_type = SPICE_MODEL_GATE_OR;
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}
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/* Get the circuit model of the gate */
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CircuitModelId gate_model = circuit_lib.port_tri_state_model(lut_input_ports[0]);
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/* Check this is the gate we want ! */
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VTR_ASSERT (required_gate_type == circuit_lib.gate_type(gate_model));
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/* Prepare for the gate instanciation */
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/* Get the input ports from the gate */
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std::vector<CircuitPortId> gate_input_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_INPUT, true);
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/* Get the output ports from the gate */
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std::vector<CircuitPortId> gate_output_ports = circuit_lib.model_ports_by_type(gate_model, SPICE_MODEL_PORT_OUTPUT, true);
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/* Check the port sizes and width:
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* we should have only 2 input ports, each of which has a size of 1
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* we should have only 1 output port, each of which has a size of 1
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*/
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VTR_ASSERT (2 == gate_input_ports.size());
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for (const auto& port : gate_input_ports) {
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VTR_ASSERT (1 == circuit_lib.port_size(port));
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}
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VTR_ASSERT (1 == gate_output_ports.size());
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for (const auto& port : gate_output_ports) {
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VTR_ASSERT (1 == circuit_lib.port_size(port));
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}
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/* Find the module id of gate_model in the module manager */
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ModuleId gate_module_id = module_manager.find_module(circuit_lib.model_name(gate_model));
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/* We must have a valid id */
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VTR_ASSERT (ModuleId::INVALID() != gate_module_id);
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/* Create a port-to-port map:
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* Input[0] of the gate is wired to a SRAM mode-select port
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* Input[1] of the gate is wired to the input port of LUT
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* Output[0] of the gate is wired to the mode_select_output_port
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*/
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std::map<std::string, BasicPort> port2port_name_map;
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port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[0])] = cur_lut_mode_select_sram_port;
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port2port_name_map[circuit_lib.port_lib_name(gate_input_ports[1])] = cur_input_port;
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port2port_name_map[circuit_lib.port_lib_name(gate_output_ports[0])] = cur_mode_select_output_port;
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/* Instanciate the gate */
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print_verilog_module_instance(fp, module_manager, module_id, gate_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
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/* IMPORTANT: this update MUST be called after the instance outputting!!!!
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* update the module manager with the relationship between the parent and child modules
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*/
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module_manager.add_child_module(module_id, gate_module_id);
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/* update the lsb of mode select port size */
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mode_select_port_lsb++;
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}
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print_verilog_comment(fp, std::string("---- END Instanciation of model-select gates -----"));
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/* Sanitity check */
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if ( true == circuit_lib.is_lut_fracturable(circuit_model) ) {
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if (mode_select_port_lsb != circuit_lib.port_size(lut_mode_select_sram_ports[0])) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"(FILE:%s,LINE[%d]) Circuit model LUT (name=%s) has a unmatched tri-state map (%s) implied by mode_port size(%d)!\n",
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__FILE__, __LINE__,
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circuit_lib.model_name(circuit_model).c_str(),
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tri_state_map.c_str(),
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circuit_lib.port_size(lut_mode_select_sram_ports[0]));
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exit(1);
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}
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}
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/* Add a blank-line splitter */
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fp << std::endl;
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/* Add inverters to mode_select output ports */
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|
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input inverters modules -----"));
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|
|
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/* Find the circuit model of the input inverter */
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|
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CircuitModelId input_inverter_model = circuit_lib.lut_input_inverter_model(circuit_model);
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VTR_ASSERT( CircuitModelId::INVALID() != input_inverter_model );
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|
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/* Now we need to add inverters by instanciating the modules */
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|
|
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for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) {
|
|
|
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/* Input of inverter is the output of mode select circuits */
|
|
|
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BasicPort inverter_instance_input_port(mode_select_output_port.get_name(), pin, pin);
|
|
|
|
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/* Output of inverter is the inverted input port */
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|
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BasicPort inverter_instance_output_port(inverted_input_port.get_name(), pin, pin);
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print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_inverter_model, inverter_instance_input_port, inverter_instance_output_port);
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}
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|
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print_verilog_comment(fp, std::string("---- END Instanciation of an input inverters modules -----"));
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|
|
|
|
|
|
|
|
|
/* Add buffers to mode_select output ports */
|
|
|
|
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print_verilog_comment(fp, std::string("---- BEGIN Instanciation of an input buffer modules -----"));
|
|
|
|
|
/* Find the circuit model of the input inverter */
|
|
|
|
|
CircuitModelId input_buffer_model = circuit_lib.lut_input_buffer_model(circuit_model);
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|
|
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VTR_ASSERT( CircuitModelId::INVALID() != input_buffer_model );
|
|
|
|
|
/* Now we need to add inverters by instanciating the modules */
|
|
|
|
|
for (const auto& pin : circuit_lib.pins(lut_input_ports[0])) {
|
|
|
|
|
/* Input of inverter is the output of mode select circuits */
|
|
|
|
|
BasicPort buffer_instance_input_port(mode_select_output_port.get_name(), pin, pin);
|
|
|
|
|
/* Output of inverter is the inverted input port */
|
|
|
|
|
BasicPort buffer_instance_output_port(buffered_input_port.get_name(), pin, pin);
|
|
|
|
|
|
|
|
|
|
print_verilog_buffer_instance(fp, module_manager, circuit_lib, module_id, input_buffer_model, buffer_instance_input_port, buffer_instance_output_port);
|
|
|
|
|
}
|
|
|
|
|
print_verilog_comment(fp, std::string("---- END Instanciation of an input buffer modules -----"));
|
|
|
|
|
|
|
|
|
|
/* Instanciate the multiplexing structure for the LUT */
|
|
|
|
|
print_verilog_comment(fp, std::string("---- BEGIN Instanciation of LUT multiplexer module -----"));
|
|
|
|
|
/* Find the name of LUT MUX: no need to provide a mux size, just give an invalid number (=-1) */
|
|
|
|
|
std::string lut_mux_module_name = generate_verilog_mux_subckt_name(circuit_lib, circuit_model, size_t(-1), std::string(""));
|
|
|
|
|
/* Find the module id of LUT MUX in the module manager */
|
|
|
|
|
ModuleId lut_mux_module_id = module_manager.find_module(lut_mux_module_name);
|
|
|
|
|
/* We must have a valid id */
|
|
|
|
|
VTR_ASSERT (ModuleId::INVALID() != lut_mux_module_id);
|
|
|
|
|
/* Create a port-to-port map:
|
|
|
|
|
* Input of the LUT MUX is wired to a regular SRAM port of LUT
|
|
|
|
|
* Outputs of the LUT MUX is wired to the output ports of LUT by name
|
|
|
|
|
* SRAM of the LUT MUX is wired to the buffered input port of LUT
|
|
|
|
|
* SRAM_inv of the LUT MUX is wired to the inverted input port of LUT
|
|
|
|
|
*/
|
|
|
|
|
std::map<std::string, BasicPort> port2port_name_map;
|
|
|
|
|
port2port_name_map[circuit_lib.port_lib_name(lut_input_ports[0])] = BasicPort(circuit_lib.port_lib_name(lut_regular_sram_ports[0]), circuit_lib.port_size(lut_regular_sram_ports[0]));
|
|
|
|
|
/* Skip the output ports, if we do not need a new name for the port of instance */
|
|
|
|
|
port2port_name_map[circuit_lib.port_lib_name(lut_regular_sram_ports[0])] = buffered_input_port;
|
|
|
|
|
/* TODO: be more flexible in naming !!! */
|
|
|
|
|
port2port_name_map[std::string(circuit_lib.port_lib_name(lut_regular_sram_ports[0]) + "_inv")] = inverted_input_port;
|
|
|
|
|
|
|
|
|
|
/* Instanciate the gate */
|
|
|
|
|
print_verilog_module_instance(fp, module_manager, module_id, lut_mux_module_id, port2port_name_map, circuit_lib.dump_explicit_port_map(circuit_model));
|
|
|
|
|
/* IMPORTANT: this update MUST be called after the instance outputting!!!!
|
|
|
|
|
* update the module manager with the relationship between the parent and child modules
|
|
|
|
|
*/
|
|
|
|
|
module_manager.add_child_module(module_id, lut_mux_module_id);
|
|
|
|
|
|
|
|
|
|
/* Print timing info */
|
|
|
|
|
print_verilog_submodule_timing(fp, circuit_lib, circuit_model);
|
|
|
|
|
|
|
|
|
|
/* Print signal initialization */
|
|
|
|
|
print_verilog_submodule_signal_init(fp, circuit_lib, circuit_model);
|
|
|
|
|
|
|
|
|
|
/* Put an end to the Verilog module */
|
|
|
|
|
print_verilog_module_end(fp, circuit_lib.model_name(circuit_model));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/********************************************************************
|
|
|
|
|
* Print Verilog modules for the Look-Up Tables (LUTs)
|
|
|
|
|
* in the circuit library
|
|
|
|
|
********************************************************************/
|
|
|
|
|
void print_verilog_submodule_luts(ModuleManager& module_manager,
|
|
|
|
|
const CircuitLibrary& circuit_lib,
|
|
|
|
|
const std::string& verilog_dir,
|
|
|
|
|
const std::string& submodule_dir) {
|
|
|
|
|
/* TODO: remove .bak when this part is completed and tested */
|
|
|
|
|
std::string verilog_fname = submodule_dir + luts_verilog_file_name + ".bak";
|
|
|
|
|
|
|
|
|
|
std::fstream fp;
|
|
|
|
|
|
|
|
|
|
/* Create the file stream */
|
|
|
|
|
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
|
|
|
|
|
/* Check if the file stream if valid or not */
|
|
|
|
|
check_file_handler(fp);
|
|
|
|
|
|
|
|
|
|
/* Create file */
|
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO,
|
|
|
|
|
"Generating Verilog netlist for LUTs (%s)...\n",
|
|
|
|
|
__FILE__, __LINE__, verilog_fname.c_str());
|
|
|
|
|
|
|
|
|
|
print_verilog_file_header(fp, "Look-Up Tables");
|
|
|
|
|
|
|
|
|
|
print_verilog_include_defines_preproc_file(fp, verilog_dir);
|
|
|
|
|
|
|
|
|
|
/* Search for each LUT circuit model */
|
|
|
|
|
for (const auto& circuit_model : circuit_lib.models()) {
|
|
|
|
|
/* Bypass user-defined and non-LUT modules */
|
|
|
|
|
if ( (!circuit_lib.model_verilog_netlist(circuit_model).empty())
|
|
|
|
|
|| (SPICE_MODEL_LUT != circuit_lib.model_type(circuit_model)) ) {
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
print_verilog_submodule_lut(module_manager, circuit_lib, fp, circuit_model);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Close the file handler */
|
|
|
|
|
fp.close();
|
|
|
|
|
|
|
|
|
|
/* Add fname to the linked list */
|
|
|
|
|
/* Add it when the Verilog generation is refactored
|
|
|
|
|
submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str());
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
tangxifan