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[engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols

This commit is contained in:
tangxifan 2022-09-14 16:46:10 -07:00
parent 0425b00af5
commit 036933dc14
2 changed files with 7 additions and 7 deletions
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6
openfpga/src/fabric/build_top_module_memory.cpp
View File

@ -1055,7 +1055,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
} }
VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module); VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module); size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module);
module_manager.add_child_module(top_module, bl_decoder_module); module_manager.add_child_module(top_module, bl_decoder_module, false);
/************************************************************** /**************************************************************
* Add the WL decoder module * Add the WL decoder module
@ -1083,7 +1083,7 @@ void add_top_module_nets_cmos_memory_bank_config_bus(ModuleManager& module_manag
} }
VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module); VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module); size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module);
module_manager.add_child_module(top_module, wl_decoder_module); module_manager.add_child_module(top_module, wl_decoder_module, false);
/************************************************************** /**************************************************************
* Add module nets from the top module to BL decoder's inputs * Add module nets from the top module to BL decoder's inputs
@ -1531,7 +1531,7 @@ void add_top_module_nets_cmos_memory_frame_decoder_config_bus(ModuleManager& mod
/* Instanciate the decoder module here */ /* Instanciate the decoder module here */
size_t decoder_instance = module_manager.num_instance(parent_module, decoder_module); size_t decoder_instance = module_manager.num_instance(parent_module, decoder_module);
module_manager.add_child_module(parent_module, decoder_module); module_manager.add_child_module(parent_module, decoder_module, false);
/* Connect the enable (EN) port of memory modules under the parent module /* Connect the enable (EN) port of memory modules under the parent module
* to the frame decoder inputs * to the frame decoder inputs

8
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -507,7 +507,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_decoder_config_bus(ModuleManager
} }
VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module); VTR_ASSERT(ModuleId::INVALID() != bl_decoder_module);
size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module); size_t curr_bl_decoder_instance_id = module_manager.num_instance(top_module, bl_decoder_module);
module_manager.add_child_module(top_module, bl_decoder_module); module_manager.add_child_module(top_module, bl_decoder_module, false);
/************************************************************** /**************************************************************
* Add module nets from the top module to BL decoder's inputs * Add module nets from the top module to BL decoder's inputs
@ -705,7 +705,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_decoder_config_bus(ModuleManager
} }
VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module); VTR_ASSERT(ModuleId::INVALID() != wl_decoder_module);
size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module); size_t curr_wl_decoder_instance_id = module_manager.num_instance(top_module, wl_decoder_module);
module_manager.add_child_module(top_module, wl_decoder_module); module_manager.add_child_module(top_module, wl_decoder_module, false);
/************************************************************** /**************************************************************
* Add module nets from the top module to WL decoder's inputs * Add module nets from the top module to WL decoder's inputs
@ -1471,7 +1471,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
VTR_ASSERT(sr_bank_module); VTR_ASSERT(sr_bank_module);
size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module); size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module);
module_manager.add_child_module(top_module, sr_bank_module); module_manager.add_child_module(top_module, sr_bank_module, false);
sr_banks.link_bl_shift_register_bank_to_module(config_region, sr_bank, sr_bank_module); sr_banks.link_bl_shift_register_bank_to_module(config_region, sr_bank, sr_bank_module);
sr_banks.link_bl_shift_register_bank_to_instance(config_region, sr_bank, cur_inst); sr_banks.link_bl_shift_register_bank_to_instance(config_region, sr_bank, cur_inst);
@ -1565,7 +1565,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
VTR_ASSERT(sr_bank_module); VTR_ASSERT(sr_bank_module);
size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module); size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module);
module_manager.add_child_module(top_module, sr_bank_module); module_manager.add_child_module(top_module, sr_bank_module, false);
sr_banks.link_wl_shift_register_bank_to_module(config_region, sr_bank, sr_bank_module); sr_banks.link_wl_shift_register_bank_to_module(config_region, sr_bank, sr_bank_module);
sr_banks.link_wl_shift_register_bank_to_instance(config_region, sr_bank, cur_inst); sr_banks.link_wl_shift_register_bank_to_instance(config_region, sr_bank, cur_inst);