From 02e21d115b318dc3423ba87ebe93a9cceed7fddd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 10:00:12 -0600 Subject: [PATCH] [Documentation] Update 3-rd party tool version requirements --- docs/source/tutorials/tools.rst | 48 +++++++++++++++++---------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/docs/source/tutorials/tools.rst b/docs/source/tutorials/tools.rst index 0d22041d3..c332d602a 100644 --- a/docs/source/tutorials/tools.rst +++ b/docs/source/tutorials/tools.rst @@ -22,26 +22,28 @@ Third-Party Tools OpenFPGA accepts and outputs in standard file formats, and therefore can interface a wide range of commercial and open-source tools. -+--------------+-------------------------+ -| Usage | Tools | -+==============+=========================+ -| Backend | Synopsys IC Compiler II | -| | | -| | Cadence Innovus | -+--------------+-------------------------+ -| Timing | Synopsys PrimeTime | -| Analyzer | | -| | Cadence Tempus | -+--------------+-------------------------+ -| Verification | Synopsys VCS | -| | | -| | Synopsys Formality | -| | | -| | Mentor ModelSim | -| | | -| | Mentor QuestaSim | -| | | -| | Cadence NCSim | -| | | -| | Icarus iVerilog | -+--------------+-------------------------+ ++--------------+-------------------------+---------------------+ +| Usage | Tools | Version Requirement | ++==============+=========================+=====================+ +| Backend | Synopsys IC Compiler II | v2019.03 or later | +| | | | +| | Cadence Innovus | v19.1 or later | ++--------------+-------------------------+---------------------+ +| Timing | Synopsys PrimeTime | v2019.03 or later | +| Analyzer | | | +| | Cadence Tempus | v19.15 or later | ++--------------+-------------------------+---------------------+ +| Verification | Synopsys VCS | v2019.06 or later | +| | | | +| | Synopsys Formality | v2019.03 or later | +| | | | +| | Mentor ModelSim | v10.6 or later | +| | | | +| | Mentor QuestaSim | v2019.3 or later | +| | | | +| | Cadence NCSim | v15.2 or later | +| | | | +| | Icarus iVerilog | v10.1 or later | ++--------------+-------------------------+---------------------+ + +* The version requirements is based on our local tests. Older versions may work.