diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index fb94bc238..92f1b90b2 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -73,6 +73,13 @@ void rec_build_vpr_pb_graph_interconnect_physical_type_annotation(t_pb_graph_nod
/* For each interconnect that has more than 1 input, we can infer the physical type */
for (t_interconnect* interc : pb_mode_interconnects(child_physical_mode)) {
+ /* If the number inputs for an interconnect is zero, this is a 0-driver pin
+ * we just set 1 to use direct wires
+ */
+ if (0 == interc_num_inputs[interc]) {
+ interc_num_inputs[interc] = 1;
+ }
+
e_interconnect interc_physical_type = pb_interconnect_physical_type(interc, interc_num_inputs[interc]);
if (interc_physical_type == vpr_pb_type_annotation.interconnect_physical_type(interc)) {
/* Skip annotation if we have already done! */
@@ -383,7 +390,7 @@ void rec_build_vpr_physical_pb_graph_node_annotation(t_pb_graph_node* pb_graph_n
* (size_t)vpr_pb_type_annotation.pb_graph_node_unique_index(pb_graph_node)
+ vpr_pb_type_annotation.physical_pb_type_index_offset(pb_graph_node->pb_type)
);
- t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(pb_graph_node->pb_type, physical_pb_graph_node_id);
+ t_pb_graph_node* physical_pb_graph_node = vpr_pb_type_annotation.pb_graph_node(physical_pb_type, physical_pb_graph_node_id);
VTR_ASSERT(nullptr != physical_pb_graph_node);
vpr_pb_type_annotation.add_physical_pb_graph_node(pb_graph_node, physical_pb_graph_node);
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index fb2905637..8dc89251a 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -220,7 +220,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
return false;
}
/* If the port range does not match, mapping fails */
- if (false == expected_physical_pb_port.contained(BasicPort(physical_pb_port->name, physical_pb_port->num_pins))) {
+ if (false == BasicPort(physical_pb_port->name, physical_pb_port->num_pins).contained(expected_physical_pb_port)) {
return false;
}
/* Now, port mapping should succeed, we update the vpr_pb_type_annotation
@@ -337,7 +337,6 @@ void build_vpr_physical_pb_type_explicit_annotation(const DeviceContext& vpr_dev
VTR_LOG_ERROR("Unable to pair the operating pb_type '%s' to its physical pb_type '%s'!\n",
target_op_pb_type_names.back().c_str(),
target_phy_pb_type_names.back().c_str());
- return;
}
}
}
diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
new file mode 100644
index 000000000..b517fa24b
--- /dev/null
+++ b/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
@@ -0,0 +1,265 @@
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diff --git a/openfpga/test_script/s298_k6_frac.openfpga b/openfpga/test_script/s298_k6_frac.openfpga
new file mode 100644
index 000000000..22e74cdb1
--- /dev/null
+++ b/openfpga/test_script/s298_k6_frac.openfpga
@@ -0,0 +1,14 @@
+# Run VPR for the s298 design
+vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/s298.blif
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+
+# Annotate the OpenFPGA architecture to VPR data base
+link_openfpga_arch
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Finish and exit OpenFPGA
+exit
diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
index 4da00d67a..269384cbc 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml
@@ -24,6 +24,25 @@
that describe them.
-->
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@@ -127,6 +146,24 @@
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