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clean warnings

This commit is contained in:
tangxifan 2019-05-24 16:48:08 -06:00
parent 2c46da6888
commit 02b48d036d
9 changed files with 39 additions and 68 deletions
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14
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -296,8 +296,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix);
blif_testbench_file_path = my_strcat(src_dir_path, blif_testbench_file_name);
dump_verilog_input_blif_testbench(chomped_circuit_name, blif_testbench_file_path, src_dir_path,
num_clocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
*(Arch.spice));
/* Free */
my_free(blif_testbench_file_name);
my_free(blif_testbench_file_path);
@ -329,8 +328,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
top_testbench_file_name = my_strcat(chomped_circuit_name, top_testbench_verilog_file_postfix);
top_testbench_file_path = my_strcat(src_dir_path, top_testbench_file_name);
dump_verilog_top_testbench(sram_verilog_orgz_info, chomped_circuit_name, top_testbench_file_path,
src_dir_path, num_clocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
src_dir_path, *(Arch.spice));
/* Free */
my_free(top_testbench_file_name);
my_free(top_testbench_file_path);
@ -340,9 +338,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
formal_verification_top_netlist_file_name = my_strcat(chomped_circuit_name, formal_verification_verilog_file_postfix);
formal_verification_top_netlist_file_path = my_strcat(src_dir_path, formal_verification_top_netlist_file_name);
dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name,
formal_verification_top_netlist_file_path, src_dir_path,
num_clocks,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
formal_verification_top_netlist_file_path, src_dir_path);
/* Output script for formality */
write_formality_script(vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts,
fm_dir_path,
@ -352,7 +348,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
random_top_testbench_file_name = my_strcat(chomped_circuit_name, random_top_testbench_verilog_file_postfix);
random_top_testbench_file_path = my_strcat(src_dir_path, random_top_testbench_file_name);
dump_verilog_random_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
random_top_testbench_file_path, src_dir_path, num_clocks,
random_top_testbench_file_path, src_dir_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
/* Free */
my_free(formal_verification_top_netlist_file_name);
@ -363,7 +359,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
autocheck_top_testbench_file_name = my_strcat(chomped_circuit_name, autocheck_top_testbench_verilog_file_postfix);
autocheck_top_testbench_file_path = my_strcat(src_dir_path, autocheck_top_testbench_file_name);
dump_verilog_autocheck_top_testbench(sram_verilog_orgz_info, chomped_circuit_name,
autocheck_top_testbench_file_path, src_dir_path, num_clocks,
autocheck_top_testbench_file_path, src_dir_path,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts, *(Arch.spice));
/* Free */
my_free(autocheck_top_testbench_file_name);

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c
View File

@ -40,6 +40,8 @@
#include "verilog_top_netlist_utils.h"
#include "verilog_top_testbench.h"
#include "verilog_autocheck_top_testbench.h"
/* Local variables */
static char* autocheck_testbench_reference_output_postfix = "_benchmark";
static char* autocheck_testbench_verification_output_postfix = "_verification";
@ -348,7 +350,6 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog) {
FILE* fp = NULL;
@ -384,7 +385,7 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, num_clock, fpga_verilog_opts, verilog);
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog);
/* Add output autocheck */
dump_verilog_top_auto_testbench_check(fp);

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.h
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@ -3,7 +3,6 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog);

17
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.c
View File

@ -40,6 +40,8 @@
#include "verilog_top_netlist_utils.h"
#include "verilog_top_testbench.h"
#include "verilog_formal_random_top_testbench.h"
/* Local variables */
static char* formal_random_top_tb_postfix = "_top_formal_verification_random_tb";
static char* gfpga_postfix = "_gfpga";
@ -163,8 +165,8 @@ void dump_verilog_top_random_testbench_call_benchmark(FILE* fp,
}
static
int get_simulation_time(int num_prog_clock_cycles,
float prog_clock_period,
int get_simulation_time(//int num_prog_clock_cycles,
//float prog_clock_period,
int num_op_clock_cycles,
float op_clock_period) {
int total_time_period = 0;
@ -178,12 +180,12 @@ int get_simulation_time(int num_prog_clock_cycles,
static
void dump_verilog_timeout_and_vcd(FILE * fp,
char* circuit_name,
t_spice verilog,
t_sram_orgz_info* cur_sram_orgz_info){
t_spice verilog) {
//t_sram_orgz_info* cur_sram_orgz_info){
int simulation_time;
simulation_time = get_simulation_time(get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info),
1./verilog.spice_params.stimulate_params.prog_clock_freq,
simulation_time = get_simulation_time(//get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info),
//1./verilog.spice_params.stimulate_params.prog_clock_freq,
verilog.spice_params.meas_params.sim_num_clock_cycle,
1./verilog.spice_params.stimulate_params.op_clock_freq);
@ -348,7 +350,6 @@ void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog) {
FILE* fp = NULL;
@ -393,7 +394,7 @@ void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "`endif\n\n");
/* Add Icarus requirement */
dump_verilog_timeout_and_vcd(fp, circuit_name , verilog, cur_sram_orgz_info);
dump_verilog_timeout_and_vcd(fp, circuit_name , verilog/*, cur_sram_orgz_info*/);
/* Testbench ends*/
fprintf(fp, "endmodule\n");

1
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_formal_random_top_testbench.h
View File

@ -3,7 +3,6 @@ void dump_verilog_random_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog);

17
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c
View File

@ -39,6 +39,8 @@
#include "verilog_decoder.h"
#include "verilog_top_netlist_utils.h"
#include "verilog_top_testbench.h"
/* Dump all the global ports that are stored in the linked list */
void dump_verilog_top_testbench_global_ports(FILE* fp, t_llist* head,
enum e_dump_verilog_port_type dump_port_type) {
@ -899,7 +901,6 @@ void dump_verilog_top_testbench_stimuli_serial_version_tasks(t_sram_orgz_info* c
static
void dump_verilog_top_testbench_stimuli_serial_version(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clock,
t_spice spice) {
int inet, iblock, iopad_idx;
int found_mapped_inpad = 0;
@ -1160,12 +1161,10 @@ void dump_verilog_top_testbench_stimuli_serial_version(t_sram_orgz_info* cur_sra
*/
void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog) {
/* Only serial version is avaiable now */
dump_verilog_top_testbench_stimuli_serial_version(cur_sram_orgz_info, fp, num_clock, verilog);
dump_verilog_top_testbench_stimuli_serial_version(cur_sram_orgz_info, fp, verilog);
/*
if (TRUE == syn_verilog_opts.tb_serial_config_mode) {
} else {
@ -1254,8 +1253,6 @@ void dump_verilog_input_blif_testbench_call_top_module(FILE* fp,
/* Dump voltage stimuli for input blif nestlist */
static
void dump_verilog_input_blif_testbench_stimuli(FILE* fp,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice spice) {
int iblock, inet;
t_spice_net_info* cur_spice_net_info = NULL;
@ -1333,8 +1330,6 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog) {
FILE* fp = NULL;
char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name);
@ -1362,7 +1357,7 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, num_clock, fpga_verilog_opts, verilog);
dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog);
/* Testbench ends*/
fprintf(fp, "endmodule\n");
@ -1379,8 +1374,6 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
void dump_verilog_input_blif_testbench(char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog) {
FILE* fp = NULL;
char* title = my_strcat("FPGA Verilog Testbench for input blif netlist of Design: ", circuit_name);
@ -1407,7 +1400,7 @@ void dump_verilog_input_blif_testbench(char* circuit_name,
dump_verilog_input_blif_testbench_call_top_module(fp, circuit_name);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_input_blif_testbench_stimuli(fp, num_clock, syn_verilog_opts, verilog);
dump_verilog_input_blif_testbench_stimuli(fp, verilog);
/* Testbench ends*/
fprintf(fp, "endmodule\n");

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h
View File

@ -10,21 +10,15 @@ void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_
void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog);
void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog);
void dump_verilog_input_blif_testbench(char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog);

35
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c
View File

@ -38,9 +38,10 @@
#include "verilog_top_netlist_utils.h"
#include "verilog_top_testbench.h"
#include "verilog_verification_top_netlist.h"
static
void dump_verilog_formal_verification_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
void dump_verilog_formal_verification_top_netlist_ports(FILE* fp,
char* circuit_name) {
int iblock, cnt;
char* port_name = NULL;
@ -95,8 +96,7 @@ void dump_verilog_formal_verification_top_netlist_ports(t_sram_orgz_info* cur_sr
static
void dump_verilog_formal_verification_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
char* circuit_name) {
FILE* fp) {
char* port_name = NULL;
int num_array_bl, num_array_wl;
int bl_decoder_size, wl_decoder_size;
@ -197,8 +197,7 @@ void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_inf
* 1. operating clock
*/
static
void dump_verilog_formal_verification_top_netlist_connect_global_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
void dump_verilog_formal_verification_top_netlist_connect_global_ports(FILE* fp,
t_llist* head) {
t_llist* temp = head;
t_spice_model_port* cur_global_port = NULL;
@ -254,8 +253,7 @@ void dump_verilog_formal_verification_top_netlist_connect_global_ports(t_sram_or
/* Add stimuli for unused iopads and configuration memories */
static
void dump_verilog_formal_verification_top_netlist_connect_ios(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
void dump_verilog_formal_verification_top_netlist_connect_ios(FILE* fp) {
int iblock, jiopad, iopad_idx;
boolean* used_iopad = (boolean*) my_calloc (iopad_verilog_model->cnt, sizeof(boolean));
@ -370,16 +368,12 @@ void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_i
/* Add stimuli for unused iopads and configuration memories */
static
void dump_verilog_formal_verification_top_netlist_initialization(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog) {
FILE* fp) {
/* Connect FPGA top module global ports to constant or benchmark global signals! */
dump_verilog_formal_verification_top_netlist_connect_global_ports(cur_sram_orgz_info,
fp, global_ports_head);
dump_verilog_formal_verification_top_netlist_connect_global_ports(fp, global_ports_head);
/* Connect I/Os to benchmark I/Os or constant driver */
dump_verilog_formal_verification_top_netlist_connect_ios(cur_sram_orgz_info,
fp);
dump_verilog_formal_verification_top_netlist_connect_ios(fp);
/* Assign FPGA internal SRAM/Memory ports to bitstream values */
dump_verilog_formal_verification_top_netlist_config_bitstream(cur_sram_orgz_info,
@ -394,10 +388,7 @@ void dump_verilog_formal_verification_top_netlist_initialization(t_sram_orgz_inf
void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts fpga_verilog_opts,
t_spice verilog) {
char* verilog_dir_path) {
FILE* fp = NULL;
char* title = my_strcat("FPGA Verilog Top-level netlist in formal verification purpose of Design: ", circuit_name);
@ -418,16 +409,16 @@ void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_org
verilog_include_defines_preproc_file(fp, verilog_dir_path);
/* Start with module declaration */
dump_verilog_formal_verification_top_netlist_ports(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_formal_verification_top_netlist_ports(fp, circuit_name);
/* Define internal wires */
dump_verilog_formal_verification_top_netlist_internal_wires(cur_sram_orgz_info, fp, circuit_name);
dump_verilog_formal_verification_top_netlist_internal_wires(cur_sram_orgz_info, fp);
/* Call defined top-level module */
dump_verilog_formal_verfication_top_netlist_call_top_module(cur_sram_orgz_info, fp, circuit_name);
/* Add stimuli for reset, set, clock and iopad signals */
dump_verilog_formal_verification_top_netlist_initialization(cur_sram_orgz_info, fp, fpga_verilog_opts, verilog);
dump_verilog_formal_verification_top_netlist_initialization(cur_sram_orgz_info, fp);
/* Testbench ends*/
fprintf(fp, "endmodule\n");

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.h
View File

@ -2,8 +2,5 @@
void dump_verilog_formal_verification_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
char* circuit_name,
char* top_netlist_name,
char* verilog_dir_path,
int num_clock,
t_syn_verilog_opts syn_verilog_opts,
t_spice verilog);
char* verilog_dir_path);