diff --git a/openfpga_flow/openfpga_arch/README.md b/openfpga_flow/openfpga_arch/README.md index cdd8db5f3..b23e837ec 100644 --- a/openfpga_flow/openfpga_arch/README.md +++ b/openfpga_flow/openfpga_arch/README.md @@ -27,6 +27,7 @@ Note that an OpenFPGA architecture can be applied to multiple VPR architecture f - local\_encoder: If local encoders are used in routing multiplexer design - spyio/spypad: If spy I/Os are used - registerable\_io: If I/Os are registerable (can be either combinational or sequential) +- IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os) - stdcell: If circuit designs are built with standard cells only - tree\_mux: If routing multiplexers are built with a tree-like structure - localClkGen: The clock signal of CLB can be generated by internal programmable resources diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_openfpga.xml new file mode 100644 index 000000000..bbe32024a --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_openfpga.xml @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +