fix typo in Verilog generation
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21d0cb52bc
commit
01e075377d
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@ -1896,9 +1896,11 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp,
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rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
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rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
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rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
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rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow,
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dump_port_type); /* Dump the direction of the port ! */
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dump_port_type); /* Dump the direction of the port ! */
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if (FALSE == dump_port_type) {
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fprintf(fp, ",\n");
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fprintf(fp, ",\n");
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}
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}
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}
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}
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}
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return;
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return;
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}
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}
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@ -2241,7 +2243,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
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dump_verilog_reserved_sram_ports(fp, cur_sram_orgz_info,
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0,
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0,
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side_num_reserved_conf_bits - 1,
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side_num_reserved_conf_bits - 1,
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VERILOG_PORT_INPUT);
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VERILOG_PORT_CONKT);
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if (0 < side_num_reserved_conf_bits) {
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if (0 < side_num_reserved_conf_bits) {
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fprintf(fp, ",\n");
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fprintf(fp, ",\n");
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}
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}
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@ -2249,7 +2251,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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dump_verilog_sram_ports(fp, cur_sram_orgz_info,
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dump_verilog_sram_ports(fp, cur_sram_orgz_info,
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cur_sram_lsb,
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cur_sram_lsb,
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cur_sram_msb,
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cur_sram_msb,
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VERILOG_PORT_INPUT);
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VERILOG_PORT_CONKT);
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/* Dump ports only visible during formal verification*/
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/* Dump ports only visible during formal verification*/
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if (0 < num_conf_bits) {
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if (0 < num_conf_bits) {
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@ -2259,7 +2261,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or
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dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
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dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info,
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cur_sram_lsb,
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cur_sram_lsb,
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cur_sram_msb,
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cur_sram_msb,
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VERILOG_PORT_OUTPUT);
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VERILOG_PORT_CONKT);
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fprintf(fp, "\n");
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fprintf(fp, "\n");
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fprintf(fp, "`endif\n");
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fprintf(fp, "`endif\n");
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}
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}
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