From 2483154c342ea6220a658a8d5d8f6a3e51da0010 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 16:28:32 -0700
Subject: [PATCH 1/6] [Tool] Patch disable_packing XML syntax to be consistent
 with VPR upstream

---
 libs/libarchfpga/src/read_xml_arch_file.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index cf2dd72c3..47f10dbe7 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -1963,9 +1963,9 @@ static void ProcessMode(pugi::xml_node Parent, t_mode* mode, const bool timing_e
         mode->packable = mode->parent_pb_type->parent_mode->packable;
     }
     /* Override if user specify */
-    mode->packable = get_attribute(Parent, "packable", loc_data, ReqOpt::OPTIONAL).as_bool(mode->packable);
+    mode->packable = ~get_attribute(Parent, "disable_packing", loc_data, ReqOpt::OPTIONAL).as_bool(~mode->packable);
     if (false == mode->packable) {
-        VTR_LOG("mode '%s[%s]' is defined by user to be not packable\n",
+        VTR_LOG("mode '%s[%s]' is disabled in packing by user\n",
                  mode->parent_pb_type->name,
                  mode->name);
     }

From 66bc370c4db6bf9e151ab57a9a847947b69b10e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 16:29:03 -0700
Subject: [PATCH 2/6] [Arch] Use disable_packing in architecture library

---
 openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml     | 4 ++--
 openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml                    | 4 ++--
 openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml           | 4 ++--
 .../vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml         | 4 ++--
 .../vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml   | 4 ++--
 .../k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml       | 4 ++--
 .../k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml | 4 ++--
 openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml    | 4 ++--
 ...ble_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++--
 ...le_register_scan_chain_nonLR_embedded_io_skywater130nm.xml | 2 +-
 ...set_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++--
 ...der_register_scan_chain_nonLR_caravel_io_skywater130nm.xml | 4 ++--
 openfpga_flow/vpr_arch/k6_N10_40nm.xml                        | 2 +-
 openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml                   | 4 ++--
 openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml       | 4 ++--
 .../vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml          | 4 ++--
 openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml          | 4 ++--
 .../vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml        | 4 ++--
 ...c_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml | 4 ++--
 .../vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml | 4 ++--
 .../k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml      | 4 ++--
 ...N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml | 4 ++--
 ...6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml | 4 ++--
 .../k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml     | 4 ++--
 ...frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml | 4 ++--
 ...N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml | 4 ++--
 openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml           | 4 ++--
 27 files changed, 52 insertions(+), 52 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
index ebd08e86a..4ee4d3816 100644
--- a/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_fracNative_N4_tileable_40nm.xml
@@ -170,7 +170,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -242,7 +242,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
index 5582a8b7b..1e3760e45 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
@@ -170,7 +170,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -242,7 +242,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
index 25193bb0f..a1088d613 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
@@ -170,7 +170,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -242,7 +242,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
index 1d0a769ed..a607ab0e0 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
@@ -195,7 +195,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -271,7 +271,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
index 68f4bdcb6..ab62e6abb 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
@@ -238,7 +238,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -314,7 +314,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
index a5172d3f9..a21db338d 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
@@ -253,7 +253,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -329,7 +329,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
index eff6cc604..7a8db6837 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
@@ -265,7 +265,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -341,7 +341,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
index ce31cc671..bd2365e90 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_lutram_40nm.xml
@@ -188,7 +188,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -260,7 +260,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 8885db564..1cbb1b1c6 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -269,7 +269,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -354,7 +354,7 @@
         <output name="scout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="regin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
index 4a0f04903..47e5c806f 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_register_scan_chain_nonLR_embedded_io_skywater130nm.xml
@@ -335,7 +335,7 @@
         <output name="scout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="regin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index e7db6fd94..9586e984c 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -273,7 +273,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -360,7 +360,7 @@
         <output name="sc_out" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="reg_in" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 07c6ba848..b3b52c0f2 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -289,7 +289,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -380,7 +380,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="4"/>
             <input name="reg_in" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_40nm.xml
index 4ab67628f..e361f1160 100644
--- a/openfpga_flow/vpr_arch/k6_N10_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_N10_40nm.xml
@@ -137,7 +137,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
index 929809782..cfe91ecb0 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
@@ -163,7 +163,7 @@
       <!-- A mode denotes the physical implementation of an I/O
            This mode will be not packable but is mainly used for fabric verilog generation
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -235,7 +235,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index 8db8eadc2..8d76fd9ee 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -250,7 +250,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -326,7 +326,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 9ec50599a..796369e64 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -290,7 +290,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -366,7 +366,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
index 4eef5f3ac..442354524 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
@@ -163,7 +163,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -235,7 +235,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
index 9afc53b66..161b22e28 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -250,7 +250,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -326,7 +326,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
index 2f14a7c2f..85f7f007c 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
@@ -345,7 +345,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -428,7 +428,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
index b9bae7853..53ad0929f 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -290,7 +290,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -366,7 +366,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
index fc16bac51..0836cabfa 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -358,7 +358,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -434,7 +434,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
index b8d4b731d..1446b5643 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -327,7 +327,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -403,7 +403,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 3f29db0e9..fba62170d 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -294,7 +294,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -370,7 +370,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
index ab91d62c2..476602970 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -290,7 +290,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -366,7 +366,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
index aaf06d70c..ca9dedd1f 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
@@ -297,7 +297,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -373,7 +373,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
index 802d32ca4..4accdbd53 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
@@ -290,7 +290,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -366,7 +366,7 @@
         <output name="cout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
index f642014f7..8f98b1211 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
@@ -163,7 +163,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" disabled_in_pack="true">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -235,7 +235,7 @@
         <output name="out" num_pins="2"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <output name="out" num_pins="2"/>

From 9b5c64f35f1555569b4f4ca2627c8bf3cf73e1c4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 16:41:24 -0700
Subject: [PATCH 3/6] [Doc] Update documentation about disable_packing syntax

---
 docs/source/manual/arch_lang/addon_vpr_syntax.rst | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
index 773ac0992..84c448ba1 100644
--- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
@@ -14,13 +14,13 @@ Each ``<pb_type>`` should contain a ``<mode>`` that describe the physical implem
 
 .. note:: Currently, OpenFPGA only supports 1 ``<equivalent_sites>`` to be defined under each ``<tile>``
 
-.. option:: <mode packable="<bool">/>
+.. option:: <mode disable_packing="<bool">/>
 
-  OpenFPGA allows users to define it a mode is packable for VPR.
-  By default, the packable is set to ``true``. 
+  OpenFPGA allows users to define it a mode is disabled for VPR packer.
+  By default, the ``disable_packing`` is set to ``false``. 
   This is mainly used for the mode that describes the physical implementation, which is typically not packable. Disable it in the packing and signficantly accelerate the packing runtime.
 
-  .. note:: Once a mode is set to unpackable, its child modes will be unpackable as well.
+  .. note:: Once a mode is disabled in packing, its child modes will be disabled as well.
 
 Layout
 ~~~~~~

From 1d96974b997992d43b4429bca4a0bb4d2850b84f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 16:54:04 -0700
Subject: [PATCH 4/6] [Tool] Patch to remove compiler warnings

---
 libs/libarchfpga/src/read_xml_arch_file.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp
index 47f10dbe7..fa5c188e4 100644
--- a/libs/libarchfpga/src/read_xml_arch_file.cpp
+++ b/libs/libarchfpga/src/read_xml_arch_file.cpp
@@ -1963,7 +1963,7 @@ static void ProcessMode(pugi::xml_node Parent, t_mode* mode, const bool timing_e
         mode->packable = mode->parent_pb_type->parent_mode->packable;
     }
     /* Override if user specify */
-    mode->packable = ~get_attribute(Parent, "disable_packing", loc_data, ReqOpt::OPTIONAL).as_bool(~mode->packable);
+    mode->packable = !get_attribute(Parent, "disable_packing", loc_data, ReqOpt::OPTIONAL).as_bool(!mode->packable);
     if (false == mode->packable) {
         VTR_LOG("mode '%s[%s]' is disabled in packing by user\n",
                  mode->parent_pb_type->name,

From 3513966078b5e9bf926aa1f3feb0959a6639a1f8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 17:30:49 -0700
Subject: [PATCH 5/6] [Tool] Borrow a quick fix from the VPR pull request
 https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files

---
 vpr/src/pack/cluster.cpp | 62 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/vpr/src/pack/cluster.cpp b/vpr/src/pack/cluster.cpp
index 51de31f7e..706e82e74 100644
--- a/vpr/src/pack/cluster.cpp
+++ b/vpr/src/pack/cluster.cpp
@@ -1185,6 +1185,64 @@ static void alloc_and_load_pb_stats(t_pb* pb, const int feasible_block_array_siz
 }
 /*****************************************/
 
+/**
+ *  * Cleans up a pb after unsuccessful molecule packing
+ *   */
+static bool cleanup_pb(t_pb* pb) {
+    bool can_free = true;
+
+    /* Recursively check if there are any children with already assigned atoms */
+    if (pb->child_pbs != nullptr) {
+        const t_mode* mode = &pb->pb_graph_node->pb_type->modes[pb->mode];
+        VTR_ASSERT(mode != nullptr);
+
+        /* Check each mode */
+        for (int i = 0; i < mode->num_pb_type_children; ++i) {
+            /* Check each child */
+            if (pb->child_pbs[i] != nullptr) {
+                for (int j = 0; j < mode->pb_type_children[i].num_pb; ++j) {
+                    t_pb* pb_child = &pb->child_pbs[i][j];
+                    t_pb_type* pb_type = pb_child->pb_graph_node->pb_type;
+
+                    /* Primitive, check occupancy */
+                    if (pb_type->num_modes == 0) {
+                        if (pb_child->name != nullptr) {
+                            can_free = false;
+                        }
+                    }
+
+                    /* Non-primitive, recurse */
+                    else {
+                        if (!cleanup_pb(pb_child)) {
+                            can_free = false;
+                        }
+                    }
+                }
+            }
+        }
+
+        /* Free if can */
+        if (can_free) {
+            for (int i = 0; i < mode->num_pb_type_children; ++i) {
+                if (pb->child_pbs[i] != nullptr) {
+                    delete[] pb->child_pbs[i];
+                }
+            }
+
+            delete[] pb->child_pbs;
+            pb->child_pbs = nullptr;
+            pb->mode = 0;
+
+            if (pb->name) {
+                free(pb->name);
+                pb->name = nullptr;
+            }
+        }
+    }
+
+    return can_free;
+}
+
 /**
  * Try pack molecule into current cluster
  */
@@ -1364,6 +1422,10 @@ static enum e_block_pack_status try_pack_molecule(t_cluster_placement_stats* clu
                         revert_place_atom_block(molecule->atom_block_ids[i], router_data, atom_molecules);
                     }
                 }
+
+                /* Placement failed, clean the pb */
+                cleanup_pb(pb);
+
             } else {
                 VTR_LOGV(verbosity > 3, "\t\tPASSED pack molecule\n");
             }

From dc09c47411e4ca96fc693d855a0f7f5f51cc71b3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 18:03:56 -0700
Subject: [PATCH 6/6] [Arch] Remove packable from architecture files and
 replace with disable_packing

---
 openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml   |  2 +-
 openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml     |  2 +-
 .../k4_N4_tileable_GlobalTile4Clk_40nm.xml         |  2 +-
 .../vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml |  2 +-
 ...tileable_GlobalTileClk_registerable_io_40nm.xml |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml    |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml    |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml    |  2 +-
 .../k4_N4_tileable_full_output_crossbar_40nm.xml   |  2 +-
 .../k4_N4_tileable_no_local_routing_40nm.xml       |  2 +-
 .../k4_N5_tileable_pattern_local_routing_40nm.xml  |  2 +-
 openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml    |  2 +-
 ...frac_N10_tileable_adder_register_chain_40nm.xml |  4 ++--
 ...N10_tileable_adder_register_scan_chain_40nm.xml |  4 ++--
 ...able_adder_register_scan_chain_depop50_40nm.xml |  6 +++---
 ...der_register_scan_chain_depop50_spypad_40nm.xml | 14 +++++++-------
 ...der_register_scan_chain_mem16K_depop50_12nm.xml |  6 +++---
 17 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
index 97ffe88aa..cc7018c45 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
index 90a484880..214e81e9a 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
index 9317483be..f7b554a9f 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
@@ -147,7 +147,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
index 9d6f7d31d..507c90158 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
@@ -146,7 +146,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
index c3c68f421..22e8b5f99 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
@@ -150,7 +150,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
index fdbf7a440..02ea4876f 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
index 2a07d020d..61639716b 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
index b54749174..4d69618a5 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index 00dc13362..69c3ce124 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -145,7 +145,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index b4ebcc711..766632e30 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -148,7 +148,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
index 29c20f59a..1e8c98f19 100644
--- a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
index fcbc20437..f60bf5674 100644
--- a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
@@ -137,7 +137,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
index f98de28e6..66dc465b2 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -255,7 +255,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -335,7 +335,7 @@
         <output name="regout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 2fb64bf21..4c1b378fd 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -271,7 +271,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -355,7 +355,7 @@
         <output name="scout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index 35079cc2d..f19ffe9e9 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -223,7 +223,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -311,7 +311,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -383,7 +383,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
index e6e3c11ce..88c3f7b76 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -261,7 +261,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -349,7 +349,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -421,7 +421,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
@@ -776,7 +776,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -848,7 +848,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
@@ -1103,7 +1103,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -1175,7 +1175,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
index 2ee4db855..baada7911 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
@@ -260,7 +260,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -351,7 +351,7 @@
         <!-- Timing annotation is not require for unpackable mode
              It will not be used by timing analyzer
           -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -423,7 +423,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>