diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
index 731148c50..01ae1b929 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoder.c
@@ -404,27 +404,27 @@ void dump_verilog_membank_config_module(FILE* fp,
     assert( 0 == num_reserved_bl );
     assert( 0 == num_reserved_wl );
     /* Declare normal BL / WL inputs */
-    fprintf(fp, "  input wire [%d:%d] %s%s, //---- Normal Bit lines \n",
+    fprintf(fp, "  output wire [%d:%d] %s%s, //---- Normal Bit lines \n",
             0, num_bl - 1, mem_model->prefix, top_netlist_normal_bl_port_postfix);
-    fprintf(fp, "  input wire [%d:%d] %s%s //---- Normal Word lines\n",
+    fprintf(fp, "  output wire [%d:%d] %s%s",
             0, num_wl - 1, mem_model->prefix, top_netlist_normal_wl_port_postfix);
     /* Declare inverted wires if needed */
     if (1 == num_blb_ports) {
-      fprintf(fp, ",  \n");
+      fprintf(fp, ",  //---- Normal Word lines \n");
     } else {
-      fprintf(fp, ");\n");
+      fprintf(fp, "  //---- Normal Word lines\n);\n");
     }
     if (1 == num_blb_ports) {
-      fprintf(fp, " input wire [%d:%d] %s%s //---- Inverted Normal Bit lines \n",
+      fprintf(fp, " output wire [%d:%d] %s%s",
               0, num_bl - 1, mem_model->prefix, top_netlist_normal_blb_port_postfix);
     }
     if (1 == num_wlb_ports) {
-      fprintf(fp, ",  \n");
+      fprintf(fp, ", //---- Inverted Normal Bit lines \n");
     } else {
-      fprintf(fp, ");\n");
+      fprintf(fp, " //---- Inverted Normal Bit lines \n);\n");
     }
     if (1 == num_wlb_ports) {
-      fprintf(fp, " input wire [%d:%d] %s%s //---- Inverted Normal Word lines \n",
+      fprintf(fp, " output wire [%d:%d] %s%s //---- Inverted Normal Word lines \n",
               0, num_wl - 1, mem_model->prefix, top_netlist_normal_wlb_port_postfix);
       fprintf(fp, ");\n");
     }