diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 3c2861282..dcd6e828f 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -38,10 +38,9 @@ std::vector ClockNetwork::levels( return ret; } -std::vector ClockNetwork::pins(const ClockTreeId& tree_id, - const ClockLevelId& level, - const t_rr_type& track_type, - const Direction& direction) const { +std::vector ClockNetwork::pins( + const ClockTreeId& tree_id, const ClockLevelId& level, + const t_rr_type& track_type, const Direction& direction) const { std::vector ret; /* Avoid to repeatedly count the tracks which can be shared by spines * For two or more spines that locate in different coordinates, they can share @@ -56,7 +55,8 @@ std::vector ClockNetwork::pins(const ClockTreeId& tree_id, if (spine_track_type(curr_spine) == track_type) { if (!dir_flags && spine_direction(curr_spine) == direction) { ret.reserve(ret.size() + tree_width(spine_parent_trees_[curr_spine])); - for (size_t i = 0; i < tree_width(spine_parent_trees_[curr_spine]); ++i) { + for (size_t i = 0; i < tree_width(spine_parent_trees_[curr_spine]); + ++i) { ret.push_back(ClockTreePinId(i)); } dir_flags = true; @@ -66,8 +66,6 @@ std::vector ClockNetwork::pins(const ClockTreeId& tree_id, return ret; } - - /************************************************************************ * Public Accessors : Basic data query ***********************************************************************/ diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 793da08d5..60250af86 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -53,10 +53,12 @@ class ClockNetwork { std::vector levels(const ClockTreeId& tree_id) const; /* Return a list of spine id under a clock tree */ std::vector spines(const ClockTreeId& tree_id) const; - /* Return a list of clock pins in a bus of clock tree at a given level and direction */ - std::vector pins(const ClockTreeId& tree_id, const ClockLevelId& level, - const t_rr_type& track_type, - const Direction& direction) const; + /* Return a list of clock pins in a bus of clock tree at a given level and + * direction */ + std::vector pins(const ClockTreeId& tree_id, + const ClockLevelId& level, + const t_rr_type& track_type, + const Direction& direction) const; public: /* Public Accessors: Basic data query */ /* Return the number of routing tracks required by a selected clock tree at a diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp index cc6fe98c4..adbba8399 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.cpp @@ -1,99 +1,97 @@ -#include "vtr_assert.h" -#include "vtr_log.h" #include "rr_clock_spatial_lookup.h" -namespace openfpga { // begin namespace openfpga +#include "vtr_assert.h" +#include "vtr_log.h" -RRClockSpatialLookup::RRClockSpatialLookup() { +namespace openfpga { // begin namespace openfpga + +RRClockSpatialLookup::RRClockSpatialLookup() {} + +RRNodeId RRClockSpatialLookup::find_node(int x, int y, const ClockTreeId& tree, + const ClockLevelId& lvl, + const ClockTreePinId& pin, + const Direction& direction) const { + size_t dir = size_t(direction); + /* Pre-check: the x, y, side and ptc should be non negative numbers! + * Otherwise, return an invalid id */ + if ((x < 0) || (y < 0) || + (direction != Direction::INC && direction != Direction::DEC)) { + return RRNodeId::INVALID(); + } + + /* Sanity check to ensure the x, y, side and ptc are in range + * - Return an valid id by searching in look-up when all the parameters are in + * range + * - Return an invalid id if any out-of-range is detected + */ + if (size_t(dir) >= rr_node_indices_.size()) { + return RRNodeId::INVALID(); + } + + if (size_t(x) >= rr_node_indices_[dir].dim_size(0)) { + return RRNodeId::INVALID(); + } + + if (size_t(y) >= rr_node_indices_[dir].dim_size(1)) { + return RRNodeId::INVALID(); + } + + auto result_tree = rr_node_indices_[dir][x][y].find(tree); + if (result_tree == rr_node_indices_[dir][x][y].end()) { + return RRNodeId::INVALID(); + } + + auto result_lvl = result_tree->second.find(lvl); + if (result_lvl == result_tree->second.end()) { + return RRNodeId::INVALID(); + } + + auto result_pin = result_lvl->second.find(pin); + if (result_pin == result_lvl->second.end()) { + return RRNodeId::INVALID(); + } + + return result_pin->second; } -RRNodeId RRClockSpatialLookup::find_node(int x, - int y, - const ClockTreeId& tree, - const ClockLevelId& lvl, - const ClockTreePinId& pin, - const Direction& direction) const { - size_t dir = size_t(direction); - /* Pre-check: the x, y, side and ptc should be non negative numbers! Otherwise, return an invalid id */ - if ((x < 0) || (y < 0) || (direction != Direction::INC && direction != Direction::DEC)) { - return RRNodeId::INVALID(); - } - - /* Sanity check to ensure the x, y, side and ptc are in range - * - Return an valid id by searching in look-up when all the parameters are in range - * - Return an invalid id if any out-of-range is detected - */ - if (size_t(dir) >= rr_node_indices_.size()) { - return RRNodeId::INVALID(); - } - - if (size_t(x) >= rr_node_indices_[dir].dim_size(0)) { - return RRNodeId::INVALID(); - } - - if (size_t(y) >= rr_node_indices_[dir].dim_size(1)) { - return RRNodeId::INVALID(); - } - - auto result_tree = rr_node_indices_[dir][x][y].find(tree); - if (result_tree == rr_node_indices_[dir][x][y].end()) { - return RRNodeId::INVALID(); - } - - auto result_lvl = result_tree->second.find(lvl); - if (result_lvl == result_tree->second.end()) { - return RRNodeId::INVALID(); - } - - auto result_pin = result_lvl->second.find(pin); - if (result_pin == result_lvl->second.end()) { - return RRNodeId::INVALID(); - } - - return result_pin->second; -} - - -void RRClockSpatialLookup::add_node(RRNodeId node, - int x, - int y, +void RRClockSpatialLookup::add_node(RRNodeId node, int x, int y, const ClockTreeId& tree, const ClockLevelId& lvl, const ClockTreePinId& pin, const Direction& direction) { - size_t dir = size_t(direction); - VTR_ASSERT(node); /* Must have a valid node id to be added */ - VTR_ASSERT_SAFE(2 == rr_node_indices_[dir].ndims()); + size_t dir = size_t(direction); + VTR_ASSERT(node); /* Must have a valid node id to be added */ + VTR_ASSERT_SAFE(2 == rr_node_indices_[dir].ndims()); - resize_nodes(x, y, direction); + resize_nodes(x, y, direction); - /* Resize on demand finished; Register the node */ - rr_node_indices_[dir][x][y][tree][lvl][pin] = node; + /* Resize on demand finished; Register the node */ + rr_node_indices_[dir][x][y][tree][lvl][pin] = node; } -void RRClockSpatialLookup::resize_nodes(int x, - int y, +void RRClockSpatialLookup::resize_nodes(int x, int y, const Direction& direction) { - /* Expand the fast look-up if the new node is out-of-range - * This may seldom happen because the rr_graph building function - * should ensure the fast look-up well organized - */ - size_t dir = size_t(direction); - VTR_ASSERT(dir < rr_node_indices_.size()); - VTR_ASSERT(x >= 0); - VTR_ASSERT(y >= 0); + /* Expand the fast look-up if the new node is out-of-range + * This may seldom happen because the rr_graph building function + * should ensure the fast look-up well organized + */ + size_t dir = size_t(direction); + VTR_ASSERT(dir < rr_node_indices_.size()); + VTR_ASSERT(x >= 0); + VTR_ASSERT(y >= 0); - if ((x >= int(rr_node_indices_[dir].dim_size(0))) - || (y >= int(rr_node_indices_[dir].dim_size(1)))) { - rr_node_indices_[dir].resize({std::max(rr_node_indices_[dir].dim_size(0), size_t(x) + 1), - std::max(rr_node_indices_[dir].dim_size(1), size_t(y) + 1)}); - } + if ((x >= int(rr_node_indices_[dir].dim_size(0))) || + (y >= int(rr_node_indices_[dir].dim_size(1)))) { + rr_node_indices_[dir].resize( + {std::max(rr_node_indices_[dir].dim_size(0), size_t(x) + 1), + std::max(rr_node_indices_[dir].dim_size(1), size_t(y) + 1)}); + } } void RRClockSpatialLookup::clear() { - for (auto& data : rr_node_indices_) { - data.clear(); - } + for (auto& data : rr_node_indices_) { + data.clear(); + } } -} // end namespace openfpga +} // end namespace openfpga diff --git a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h index fe5b9e91f..4e1ec0f9b 100644 --- a/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h +++ b/libs/libclkarchopenfpga/src/base/rr_clock_spatial_lookup.h @@ -1,102 +1,111 @@ #ifndef RR_CLOCK_SPATIAL_LOOKUP_H #define RR_CLOCK_SPATIAL_LOOKUP_H -/** +/** * @file - * @brief This RRClockSpatialLookup class encapsulates + * @brief This RRClockSpatialLookup class encapsulates * the node-lookup for clock nodes in a routing resource graph * - * A data structure built to find the id of an routing resource node - * (rr_node) given information about its physical position and type in a clock network - * The data structure is mostly needed during building the clock part of a routing resource graph + * A data structure built to find the id of an routing resource node + * (rr_node) given information about its physical position and type in a clock + * network The data structure is mostly needed during building the clock part of + * a routing resource graph * - * The data structure allows users to + * The data structure allows users to * * - Update the look-up with new nodes * - Find the id of a node with given information, e.g., x, y, type etc. */ +#include "clock_network_fwd.h" +#include "physical_types.h" +#include "rr_graph_fwd.h" +#include "rr_node_types.h" #include "vtr_geometry.h" #include "vtr_vector.h" -#include "physical_types.h" -#include "rr_node_types.h" -#include "rr_graph_fwd.h" -#include "clock_network_fwd.h" -namespace openfpga { // begin namespace openfpga +namespace openfpga { // begin namespace openfpga class RRClockSpatialLookup { - /* -- Constructors -- */ - public: - /* Explicitly define the only way to create an object */ - explicit RRClockSpatialLookup(); + /* -- Constructors -- */ + public: + /* Explicitly define the only way to create an object */ + explicit RRClockSpatialLookup(); - /* Disable copy constructors and copy assignment operator - * This is to avoid accidental copy because it could be an expensive operation considering that the - * memory footprint of the data structure could ~ Gb - * Using the following syntax, we prohibit accidental 'pass-by-value' which can be immediately caught - * by compiler - */ - RRClockSpatialLookup(const RRClockSpatialLookup&) = delete; - void operator=(const RRClockSpatialLookup&) = delete; + /* Disable copy constructors and copy assignment operator + * This is to avoid accidental copy because it could be an expensive operation + * considering that the memory footprint of the data structure could ~ Gb + * Using the following syntax, we prohibit accidental 'pass-by-value' which + * can be immediately caught by compiler + */ + RRClockSpatialLookup(const RRClockSpatialLookup&) = delete; + void operator=(const RRClockSpatialLookup&) = delete; - /* -- Accessors -- */ - public: - /** - * @brief Returns the index of the specified routing resource node. - * - * @param (x, y) are the grid location within the FPGA - * @param clk_tree specifies the id of the clock tree in a clock network, - * @param clk_level specifies the level of the clock node in a clock network (typically multi-level), - * @param clk_pin specifies the pin id of the clock node in a bus of clock tree (consider multiple clock in a tree) - * @param direction specifies how the clock node will propagate the signal (either in a horizental or a vertical way) - * - * @note An invalid id will be returned if the node does not exist - */ - RRNodeId find_node(int x, - int y, - const ClockTreeId& tree, - const ClockLevelId& lvl, - const ClockTreePinId& pin, - const Direction& direction) const; + /* -- Accessors -- */ + public: + /** + * @brief Returns the index of the specified routing resource node. + * + * @param (x, y) are the grid location within the FPGA + * @param clk_tree specifies the id of the clock tree in a clock network, + * @param clk_level specifies the level of the clock node in a clock network + * (typically multi-level), + * @param clk_pin specifies the pin id of the clock node in a bus of clock + * tree (consider multiple clock in a tree) + * @param direction specifies how the clock node will propagate the signal + * (either in a horizental or a vertical way) + * + * @note An invalid id will be returned if the node does not exist + */ + RRNodeId find_node(int x, int y, const ClockTreeId& tree, + const ClockLevelId& lvl, const ClockTreePinId& pin, + const Direction& direction) const; - /* -- Mutators -- */ - public: - /** - * @brief Register a node in the fast look-up - * - * @note You must have a valid node id to register the node in the lookup - * - * @param (x, y) are the grid location within the FPGA - * @param clk_tree specifies the id of the clock tree in a clock network, - * @param clk_level specifies the level of the clock node in a clock network (typically multi-level), - * @param clk_pin specifies the pin id of the clock node in a bus of clock tree (consider multiple clock in a tree) - * @param direction specifies how the clock node will propagate the signal (either in a horizental or a vertical way) + /* -- Mutators -- */ + public: + /** + * @brief Register a node in the fast look-up + * + * @note You must have a valid node id to register the node in the lookup + * + * @param (x, y) are the grid location within the FPGA + * @param clk_tree specifies the id of the clock tree in a clock network, + * @param clk_level specifies the level of the clock node in a clock network + (typically multi-level), + * @param clk_pin specifies the pin id of the clock node in a bus of clock + tree (consider multiple clock in a tree) + * @param direction specifies how the clock node will propagate the signal + (either in a horizental or a vertical way) - * - * @note a node added with this call will not create a node in the rr_graph node list - * You MUST add the node in the rr_graph so that the node is valid - */ - void add_node(RRNodeId node, - int x, - int y, - const ClockTreeId& clk_tree, - const ClockLevelId& clk_lvl, - const ClockTreePinId& clk_pin, - const Direction& direction); + * + * @note a node added with this call will not create a node in the rr_graph + node list + * You MUST add the node in the rr_graph so that the node is valid + */ + void add_node(RRNodeId node, int x, int y, const ClockTreeId& clk_tree, + const ClockLevelId& clk_lvl, const ClockTreePinId& clk_pin, + const Direction& direction); - /** @brief Clear all the data inside */ - void clear(); + /** @brief Clear all the data inside */ + void clear(); - private: /* Private mutators */ - /** @brief Resize the nodes upon needs */ - void resize_nodes(int x, int y, const Direction& direction); + private: /* Private mutators */ + /** @brief Resize the nodes upon needs */ + void resize_nodes(int x, int y, const Direction& direction); - /* -- Internal data storage -- */ - private: - /* Fast look-up: [INC|DEC][0..grid_width][0..grid_height][tree_id][level_id][clock_pin_id] */ - std::array>>, 2>, 2> rr_node_indices_; + /* -- Internal data storage -- */ + private: + /* Fast look-up: + * [INC|DEC][0..grid_width][0..grid_height][tree_id][level_id][clock_pin_id] + */ + std::array< + vtr::NdMatrix< + std::map>>, + 2>, + 2> + rr_node_indices_; }; -} // end namespace openfpga +} // end namespace openfpga #endif diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 4e9489803..fe2605c5f 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -111,7 +111,8 @@ static void add_rr_graph_block_clock_nodes(RRGraphBuilder& rr_graph_builder, /* FIXME: need to set rc_index and cost_index when building the graph * in VTR */ /* register the node to a dedicated lookup */ - clk_rr_lookup.add_node(clk_node, chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir); + clk_rr_lookup.add_node(clk_node, chan_coord.x(), chan_coord.y(), + itree, ilvl, ipin, node_dir); /* Update ptc count and go to next */ curr_node_ptc++; } @@ -140,9 +141,9 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, (false == is_chanx_exist(grids, chanx_coord))) { continue; } - add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, - chanx_coord, CHANX, - CHANX_COST_INDEX_START); + add_rr_graph_block_clock_nodes(rr_graph_builder, clk_rr_lookup, + rr_graph_view, clk_ntwk, chanx_coord, + CHANX, CHANX_COST_INDEX_START); } } @@ -157,8 +158,8 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, continue; } add_rr_graph_block_clock_nodes( - rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, chany_coord, CHANY, - CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments()); + rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, chany_coord, + CHANY, CHANX_COST_INDEX_START + rr_graph_view.num_rr_segments()); } } } @@ -166,19 +167,17 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder, /******************************************************************** * Add edges for the clock nodes in a given connection block *******************************************************************/ -static -void add_rr_graph_block_clock_edges(RRGraphBuilder& rr_graph_builder, - const RRClockSpatialLookup& clk_rr_lookup, - const RRGraphView& rr_graph_view, - const ClockNetwork& clk_ntwk, - const vtr::Point chan_coord, - const t_rr_type& chan_type) { +static void add_rr_graph_block_clock_edges( + RRGraphBuilder& rr_graph_builder, const RRClockSpatialLookup& clk_rr_lookup, + const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk, + const vtr::Point chan_coord, const t_rr_type& chan_type) { for (auto itree : clk_ntwk.trees()) { for (auto ilvl : clk_ntwk.levels(itree)) { for (auto node_dir : {Direction::INC, Direction::DEC}) { for (auto ipin : clk_ntwk.pins(itree, ilvl, chan_type, node_dir)) { /* find the driver clock node through lookup */ - RRNodeId driver_node = clk_rr_lookup.find_node(chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir); + RRNodeId driver_node = clk_rr_lookup.find_node( + chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir); VTR_ASSERT(driver_node); /* TODO: find the fan-out clock node through lookup */ /* TODO: Create edges */ @@ -208,13 +207,12 @@ void add_rr_graph_block_clock_edges(RRGraphBuilder& rr_graph_builder, * v * clk0_lvl1_chany[1][1] *******************************************************************/ -static -void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, - const RRClockSpatialLookup& clk_rr_lookup, - const RRGraphView& rr_graph_view, - const DeviceGrid& grids, - const bool& through_channel, - const ClockNetwork& clk_ntwk) { +static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, + const RRClockSpatialLookup& clk_rr_lookup, + const RRGraphView& rr_graph_view, + const DeviceGrid& grids, + const bool& through_channel, + const ClockNetwork& clk_ntwk) { /* Add edges which is driven by X-direction clock routing tracks */ for (size_t iy = 0; iy < grids.height() - 1; ++iy) { for (size_t ix = 1; ix < grids.width() - 1; ++ix) { @@ -225,8 +223,9 @@ void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, (false == is_chanx_exist(grids, chanx_coord))) { continue; } - add_rr_graph_block_clock_edges(rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, - chanx_coord, CHANX); + add_rr_graph_block_clock_edges(rr_graph_builder, clk_rr_lookup, + rr_graph_view, clk_ntwk, chanx_coord, + CHANX); } } @@ -240,8 +239,9 @@ void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, (false == is_chany_exist(grids, chany_coord))) { continue; } - add_rr_graph_block_clock_edges(rr_graph_builder, clk_rr_lookup, rr_graph_view, clk_ntwk, - chany_coord, CHANY); + add_rr_graph_block_clock_edges(rr_graph_builder, clk_rr_lookup, + rr_graph_view, clk_ntwk, chany_coord, + CHANY); } } } @@ -256,8 +256,7 @@ void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder, *******************************************************************/ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const bool& verbose) { + const ClockNetwork& clk_ntwk, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Appending programmable clock network to routing resource graph"); @@ -285,8 +284,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, orig_num_nodes); /* Add clock nodes */ - add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, - clk_rr_lookup, + add_rr_graph_clock_nodes(vpr_device_ctx.rr_graph_builder, clk_rr_lookup, vpr_device_ctx.rr_graph, vpr_device_ctx.grid, vpr_device_ctx.arch->through_channel, clk_ntwk); VTR_ASSERT(num_clock_nodes + orig_num_nodes == @@ -294,10 +292,11 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx, /* TODO: Add edges between clock nodes*/ size_t num_clock_edges = 0; - add_rr_graph_clock_edges(vpr_device_ctx.rr_graph_builder, - static_cast(clk_rr_lookup), - vpr_device_ctx.rr_graph, vpr_device_ctx.grid, - vpr_device_ctx.arch->through_channel, clk_ntwk); + add_rr_graph_clock_edges( + vpr_device_ctx.rr_graph_builder, + static_cast(clk_rr_lookup), + vpr_device_ctx.rr_graph, vpr_device_ctx.grid, + vpr_device_ctx.arch->through_channel, clk_ntwk); /* TODO: Sanity checks */ diff --git a/openfpga/src/annotation/append_clock_rr_graph.h b/openfpga/src/annotation/append_clock_rr_graph.h index 8f69f37f0..635a54a79 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.h +++ b/openfpga/src/annotation/append_clock_rr_graph.h @@ -17,8 +17,7 @@ namespace openfpga { int append_clock_rr_graph(DeviceContext& vpr_device_ctx, RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const bool& verbose); + const ClockNetwork& clk_ntwk, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_context.h b/openfpga/src/base/openfpga_context.h index baf6464a6..9455ed916 100644 --- a/openfpga/src/base/openfpga_context.h +++ b/openfpga/src/base/openfpga_context.h @@ -6,7 +6,6 @@ #include "bitstream_manager.h" #include "bitstream_setting.h" #include "clock_network.h" -#include "rr_clock_spatial_lookup.h" #include "decoder_library.h" #include "device_rr_gsb.h" #include "fabric_bitstream.h" @@ -18,6 +17,7 @@ #include "netlist_manager.h" #include "openfpga_arch.h" #include "openfpga_flow_manager.h" +#include "rr_clock_spatial_lookup.h" #include "simulation_setting.h" #include "tile_direct.h" #include "vpr_bitstream_annotation.h" @@ -64,7 +64,9 @@ class OpenfpgaContext : public Context { return bitstream_setting_; } const openfpga::ClockNetwork& clock_arch() const { return clock_arch_; } - const openfpga::RRClockSpatialLookup& clock_rr_lookup() const { return clock_rr_lookup_; } + const openfpga::RRClockSpatialLookup& clock_rr_lookup() const { + return clock_rr_lookup_; + } const openfpga::VprDeviceAnnotation& vpr_device_annotation() const { return vpr_device_annotation_; } @@ -121,7 +123,9 @@ class OpenfpgaContext : public Context { return bitstream_setting_; } openfpga::ClockNetwork& mutable_clock_arch() { return clock_arch_; } - openfpga::RRClockSpatialLookup& mutable_clock_rr_lookup() { return clock_rr_lookup_; } + openfpga::RRClockSpatialLookup& mutable_clock_rr_lookup() { + return clock_rr_lookup_; + } openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; } diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 0ba411511..28612bfe7 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -198,10 +198,9 @@ int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, CommandOptionId opt_verbose = cmd.option("verbose"); - return append_clock_rr_graph(g_vpr_ctx.mutable_device(), - openfpga_ctx.mutable_clock_rr_lookup(), - openfpga_ctx.clock_arch(), - cmd_context.option_enable(cmd, opt_verbose)); + return append_clock_rr_graph( + g_vpr_ctx.mutable_device(), openfpga_ctx.mutable_clock_rr_lookup(), + openfpga_ctx.clock_arch(), cmd_context.option_enable(cmd, opt_verbose)); } } /* end namespace openfpga */