diff --git a/openfpga_flow/misc/qlf_yosys.ys b/openfpga_flow/misc/qlf_yosys.ys
index cccd220b9..b5169287e 100644
--- a/openfpga_flow/misc/qlf_yosys.ys
+++ b/openfpga_flow/misc/qlf_yosys.ys
@@ -2,5 +2,5 @@
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE}
+synth_quicklogic -blif ${OUTPUT_BLIF} -family qlf_k4n8 -top ${TOP_MODULE}