diff --git a/.travis/script.sh b/.travis/script.sh index 33391d502..dc0f1f18a 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -23,10 +23,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread #python3 openfpga_flow/scripts/run_fpga_task.py s298 echo -e "Testing multi-mode architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs - -echo -e "Testing tree-like multiplexer architectures"; -python3 openfpga_flow/scripts/run_fpga_task.py tree_like_mux --maxthreads 4 --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py multi_mode --maxthreads 4 --debug --show_thread_logs echo -e "Testing compact routing techniques"; python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf deleted file mode 100644 index 67f291319..000000000 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ /dev/null @@ -1,64 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml -arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml -arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml -arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml -arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml -#arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_verilog_explicit_mapping= -#vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= - diff --git a/openfpga_flow/tasks/multi_mode/config/task.conf b/openfpga_flow/tasks/multi_mode/config/task.conf index 5157bb235..51ff24dbd 100644 --- a/openfpga_flow/tasks/multi_mode/config/task.conf +++ b/openfpga_flow/tasks/multi_mode/config/task.conf @@ -15,16 +15,21 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch1=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +arch2=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml +arch3=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_behavioral_verilog_template.xml +arch4=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml +arch5=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_1IO_template.xml +arch6=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif [SYNTHESIS_PARAM] -bench0_top = K4n4_test -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v -bench0_chan_width = 100 +bench0_top = test_modes +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v +bench0_chan_width = 300 #[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] #fix_route_chan_width=300 @@ -38,10 +43,10 @@ bench0_chan_width = 100 #vpr_fpga_verilog_print_report_timing_tcl= #vpr_fpga_verilog_print_sdc_pnr= #vpr_fpga_verilog_print_sdc_analysis= -#vpr_fpga_x2p_compact_routing_hierarchy= +##vpr_fpga_x2p_compact_routing_hierarchy= #end_flow_with_test= -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0] +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] min_route_chan_width=1.3 vpr_fpga_verilog_include_icarus_simulator= vpr_fpga_verilog_formal_verification_top_netlist= @@ -56,3 +61,4 @@ vpr_fpga_verilog_print_sdc_analysis= #vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= + diff --git a/openfpga_flow/tasks/tree_like_mux/config/task.conf b/openfpga_flow/tasks/tree_like_mux/config/task.conf deleted file mode 100644 index e98e69a14..000000000 --- a/openfpga_flow/tasks/tree_like_mux/config/task.conf +++ /dev/null @@ -1,59 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_tree_mux_template.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.blif - -[SYNTHESIS_PARAM] -bench0_top = test_modes -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k6_N10/K6N10_test_modes.v -bench0_chan_width = 300 - -#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH] -#fix_route_chan_width=300 -#vpr_fpga_verilog_include_icarus_simulator= -#vpr_fpga_verilog_formal_verification_top_netlist= -#vpr_fpga_verilog_include_timing= -#vpr_fpga_verilog_include_signal_init= -#vpr_fpga_verilog_print_autocheck_top_testbench= -#vpr_fpga_bitstream_generator= -#vpr_fpga_verilog_print_user_defined_template= -#vpr_fpga_verilog_print_report_timing_tcl= -#vpr_fpga_verilog_print_sdc_pnr= -#vpr_fpga_verilog_print_sdc_analysis= -##vpr_fpga_x2p_compact_routing_hierarchy= -#end_flow_with_test= - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -min_route_chan_width=1.3 -vpr_fpga_verilog_include_icarus_simulator= -vpr_fpga_verilog_formal_verification_top_netlist= -vpr_fpga_verilog_include_timing= -vpr_fpga_verilog_include_signal_init= -vpr_fpga_verilog_print_autocheck_top_testbench= -vpr_fpga_bitstream_generator= -vpr_fpga_verilog_print_user_defined_template= -vpr_fpga_verilog_print_report_timing_tcl= -vpr_fpga_verilog_print_sdc_pnr= -vpr_fpga_verilog_print_sdc_analysis= -vpr_fpga_verilog_explicit_mapping= -vpr_fpga_x2p_compact_routing_hierarchy= -end_flow_with_test= -