Branches - OpenFPGA - git with a cup of tea

master

5c8a59f447 · Merge pull request #1897 from lnis-uofu/patch_update · Updated 2024-11-13 23:36:24 -06:00

xt_bitset 4533d160c5 · [core] developming default mode overwrite through bitstream setting file · Updated 2024-11-25 00:20:59 -06:00	0 1		ZIP TAR.GZ
dependabot/submodules/yosys-4b3c03d 93a499efbc · Bump yosys from `0200a76` to `4b3c03d` · Updated 2024-11-21 01:32:58 -06:00	0 1		ZIP TAR.GZ
patch_update e13fa7d7a8 · Updated Patch Count · Updated 2024-11-13 23:34:04 -06:00	1 0	Included	ZIP TAR.GZ
victor_OpenFPGA_work 44125a3217 · Merge branch 'master' into victor_OpenFPGA_work · Updated 2024-09-12 12:18:34 -05:00	231 13		ZIP TAR.GZ
xt_clkntwk 4f80b1a28a · [core] skip adding opin when it does not drive any inputs inside a gsb · Updated 2024-08-11 01:19:06 -05:00	322 1		ZIP TAR.GZ
new_repack_debug 6a1f3a1d99 · reuse the original data structure of repackdc and add constraint type ignore_net · Updated 2023-12-05 04:00:00 -06:00	1446 1		ZIP TAR.GZ
gg_dev acf983a110 · Forced unused bits to default 0 · Updated 2023-10-16 23:01:29 -05:00	1294 1		ZIP TAR.GZ
ganesh_dev 5dd0313933 · Merge branch 'master' into ganesh_dev · Updated 2023-09-05 01:34:21 -05:00	1472 13		ZIP TAR.GZ
demo_docs e796e460ae · formatted · Updated 2023-02-11 18:59:51 -06:00	2294 10		ZIP TAR.GZ
adder_test 1a6f096393 · [test] deploy the new test to fpga bitstream regression tests · Updated 2022-09-21 17:54:52 -05:00	2982 3		ZIP TAR.GZ
test_debug_tileable_rr_graph_builder 6c73e75bae · [test] help to check diff. in golden netlists · Updated 2022-09-17 12:42:49 -05:00	2996 2		ZIP TAR.GZ
pin_constraint f8cfa53f51 · update yosys plugin · Updated 2022-07-11 12:03:38 -05:00	3215 4		ZIP TAR.GZ
temp-fix-ptc-plus-win-build cf5092b7fe · Merge branch 'win32-build' into temp-fix-ptc-plus-win-build · Updated 2022-06-30 07:57:30 -05:00	3237 1		ZIP TAR.GZ
vtr_integ ac000276c5 · add vtr as submodule · Updated 2022-05-26 00:40:56 -05:00	3262 1		ZIP TAR.GZ
gg_ci_cd_dev 30f9a33749 · [Bugfix] dockerfile · Updated 2022-05-23 11:08:42 -05:00	3278 0	Included	ZIP TAR.GZ
binder 688d72c67a · Merge branch 'master' into binder · Updated 2022-05-22 23:19:22 -05:00	3312 1		ZIP TAR.GZ
repack_dc 38a81e840e · [Script] Skip analysis SDC in multi-clock benchmarks · Updated 2022-03-19 21:29:27 -05:00	3438 8		ZIP TAR.GZ
arch_exploration 8f18a9ad9a · added complete bram sizing files · Updated 2022-02-07 13:19:31 -06:00	4224 24		ZIP TAR.GZ
modify_fpga_flow_script 26afa68ce2 · Merge branch 'master' into modify_fpga_flow_script · Updated 2021-12-21 14:13:12 -06:00	4073 5		ZIP TAR.GZ
hard_logic_bitstream_annotation 4ec5c21d4c · fix CI issues · Updated 2021-12-17 06:46:56 -06:00	4094 2		ZIP TAR.GZ

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