30 lines
1.2 KiB
ReStructuredText
30 lines
1.2 KiB
ReStructuredText
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.. _fpga_bitstream_repack_design_constraints:
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Repack Design Constraints
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-------------------------
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An example of design constraints is shown as follows.
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.. code-block:: xml
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<repack_design_constraints>
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<pin_constraint pb_type="clb" pin="clk[0]" net="clk0"/>
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<pin_constraint pb_type="clb" pin="clk[1]" net="clk1"/>
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<pin_constraint pb_type="clb" pin="clk[2]" net="OPEN"/>
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<pin_constraint pb_type="clb" pin="clk[3]" net="OPEN"/>
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</repack_design_constraints>
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.. option:: pb_type="<string>"
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The pb_type name to be constrained, which should be consistent with VPR's architecture description.
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.. option:: pin="<string>"
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The pin name of the ``pb_type`` to be constrained, which should be consistent with VPR's architecture description.
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.. option:: net="<string>"
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The net name of the pin to be mapped, which should be consistent with net definition in your ``.blif`` file. The reserved word ``OPEN`` means that no net should be mapped to a given pin. Please ensure that it is not conflicted with any net names in your ``.blif`` file.
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.. warning:: Design constraints is a feature for power-users. It may cause repack to fail. It is users's responsibility to ensure proper design constraints
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