53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef CELLAIGS_H
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#define CELLAIGS_H
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct AigNode
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{
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IdString portname;
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int portbit;
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bool inverter;
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int left_parent, right_parent;
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vector<pair<IdString, int>> outports;
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AigNode();
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bool operator==(const AigNode &other) const;
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unsigned int hash() const;
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};
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struct Aig
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{
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string name;
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vector<AigNode> nodes;
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Aig(Cell *cell);
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bool operator==(const Aig &other) const;
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unsigned int hash() const;
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};
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YOSYS_NAMESPACE_END
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#endif
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