62 lines
1.6 KiB
ReStructuredText
62 lines
1.6 KiB
ReStructuredText
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.. _file_format_fabric_hierarchy_file:
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Fabric Hierarchy File (.yaml)
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----------------------------------------
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This file is generated by command :ref:`openfpga_setup_commands_write_fabric_hierarchy`
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The fabric hierarchy file aims to show module trees of a number of given roots
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This file is created for netlist manipulation and detailed floorplanning during physical design steps
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By using the options of the command :ref:`openfpga_setup_commands_write_fabric_hierarchy`, user can selectively output the module tree on their needs.
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An example of the file is shown as follows.
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.. code-block:: yaml
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fpga_top:
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tile_0__2_:
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sb_0__1_:
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mux_tree_tapbuf_size2:
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INVTX1
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const1
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tap_buf4
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mux_tree_tapbuf_basis_input2_mem1:
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- TGATE
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mux_tree_tapbuf_size2_feedthrough_mem
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sb_1__config_group_mem_size40:
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mux_tree_tapbuf_size2_mem:
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- DFF
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tile_1__2_:
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grid_io_top:
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logical_tile_io_mode_io_:
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logical_tile_io_mode_physical__iopad:
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- GPIO
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- GPIO_feedthrough_DFF_mem
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direct_interc
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In this example, the root module is ``fpga_top``.
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The child modules under ``fpga_top`` are ``tile_0__2_`` and ``tile_1__2_``.
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When multiple root modules are defined, the output could be
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.. code-block:: yaml
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sb_0__1_:
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- mux_tree_tapbuf_size2
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sb_1__0_:
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- mux_tree_tapbuf_size2
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sb_1__1_:
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- mux_tree_tapbuf_size2
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cbx_1__0_:
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- mux_tree_tapbuf_size4
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cbx_1__1_:
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- mux_tree_tapbuf_size4
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cby_0__1_:
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- mux_tree_tapbuf_size2
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- mux_tree_tapbuf_size4
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cby_1__1_:
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- mux_tree_tapbuf_size4
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