63 lines
2.4 KiB
C
63 lines
2.4 KiB
C
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#ifndef VERILOG_TESTBENCH_OPTIONS_H
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#define VERILOG_TESTBENCH_OPTIONS_H
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/********************************************************************
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* Include header files required by the data structure definition
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*******************************************************************/
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#include <string>
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/* Begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Options for Verilog Testbench generator
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* Typicall usage:
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* VerilogTestbench verilog_tb_opt();
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* // Set options
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* ...
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*
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*******************************************************************/
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class VerilogTestbenchOption {
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public: /* Public constructor */
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/* Set default options */
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VerilogTestbenchOption();
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public: /* Public accessors */
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std::string output_directory() const;
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std::string reference_verilog_file_path() const;
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bool print_formal_verification_top_netlist() const;
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bool print_preconfig_top_testbench() const;
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bool print_top_testbench() const;
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bool print_simulation_ini() const;
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std::string simulation_ini_path() const;
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bool verbose_output() const;
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public: /* Public validator */
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bool validate() const;
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public: /* Public mutators */
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void set_output_directory(const std::string& output_dir);
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/* The reference verilog file path is the key parameters that will have an impact on other options:
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* - print_preconfig_top_testbench
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* - print_top_testbench
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* If the file path is empty, the above testbench generation will not be enabled
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*/
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void set_reference_verilog_file_path(const std::string& reference_verilog_file_path);
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void set_print_formal_verification_top_netlist(const bool& enabled);
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/* The preconfig top testbench generation can be enabled only when formal verification top netlist is enabled */
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void set_print_preconfig_top_testbench(const bool& enabled);
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void set_print_top_testbench(const bool& enabled);
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void set_print_simulation_ini(const std::string& simulation_ini_path);
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void set_verbose_output(const bool& enabled);
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private: /* Internal Data */
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std::string output_directory_;
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std::string reference_verilog_file_path_;
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bool print_formal_verification_top_netlist_;
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bool print_preconfig_top_testbench_;
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bool print_top_testbench_;
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/* Print simulation ini is enabled only when the path is not empty */
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std::string simulation_ini_path_;
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bool verbose_output_;
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};
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} /* End namespace openfpga*/
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#endif
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