98 lines
3.2 KiB
C++
98 lines
3.2 KiB
C++
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/******************************************************************************
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* Memember functions for data structure VerilogTestbenchOption
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******************************************************************************/
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#include "vtr_assert.h"
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#include "verilog_testbench_options.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/**************************************************
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* Public Constructors
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*************************************************/
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VerilogTestbenchOption::VerilogTestbenchOption() {
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output_directory_.clear();
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reference_verilog_file_path_.clear();
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print_preconfig_top_testbench_ = false;
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print_formal_verification_top_netlist_ = false;
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print_top_testbench_ = false;
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simulation_ini_path_.clear();
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verbose_output_ = false;
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}
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/**************************************************
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* Public Accessors
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*************************************************/
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std::string VerilogTestbenchOption::output_directory() const {
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return output_directory_;
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}
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std::string VerilogTestbenchOption::reference_verilog_file_path() const {
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return reference_verilog_file_path_;
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}
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bool VerilogTestbenchOption::print_formal_verification_top_netlist() const {
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return print_formal_verification_top_netlist_;
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}
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bool VerilogTestbenchOption::print_preconfig_top_testbench() const {
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return print_preconfig_top_testbench_;
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}
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bool VerilogTestbenchOption::print_top_testbench() const {
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return print_top_testbench_;
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}
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bool VerilogTestbenchOption::print_simulation_ini() const {
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return !simulation_ini_path_.empty();
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}
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std::string VerilogTestbenchOption::simulation_ini_path() const {
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return simulation_ini_path_;
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}
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bool VerilogTestbenchOption::verbose_output() const {
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return verbose_output_;
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}
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/******************************************************************************
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* Private Mutators
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******************************************************************************/
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void VerilogTestbenchOption::set_output_directory(const std::string& output_dir) {
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output_directory_ = output_dir;
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}
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void VerilogTestbenchOption::set_reference_verilog_file_path(const std::string& reference_verilog_file_path) {
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reference_verilog_file_path_ = reference_verilog_file_path;
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/* Chain effect on other options:
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* Enable/disable the print_preconfig_top_testbench and print_top_testbench
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*/
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set_print_preconfig_top_testbench(print_preconfig_top_testbench_);
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set_print_top_testbench(print_top_testbench_);
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}
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void VerilogTestbenchOption::set_print_formal_verification_top_netlist(const bool& enabled) {
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print_formal_verification_top_netlist_ = enabled;
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}
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void VerilogTestbenchOption::set_print_preconfig_top_testbench(const bool& enabled) {
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print_preconfig_top_testbench_ = enabled
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&& print_formal_verification_top_netlist_
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&& (!reference_verilog_file_path_.empty());
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}
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void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {
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print_top_testbench_ = enabled && (!reference_verilog_file_path_.empty());
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}
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void VerilogTestbenchOption::set_print_simulation_ini(const std::string& simulation_ini_path) {
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simulation_ini_path_ = simulation_ini_path;
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}
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void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
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verbose_output_ = enabled;
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}
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} /* end namespace openfpga */
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