OpenFPGA/yosys/tests/asicworld/code_hdl_models_nand_switch.v

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module nand_switch(a,b,out);
input a,b;
output out;
supply0 vss;
supply1 vdd;
wire net1;
pmos p1 (vdd,out,a);
pmos p2 (vdd,out,b);
nmos n1 (vss,net1,a);
nmos n2 (net1,out,b);
endmodule