OpenFPGA/examples/example_2.blif

# Benchmark "example_2.bench" written by ABC on Wed Nov 14 11:42:18 2018
.model example_2.bench
.inputs I0 clk
.outputs Q0

.latch         n7         Q0 re        clk  0

.names I0 n7
0 1
.end
Update of the examples to correspond to the new syntax 2018-11-14 15:01:39 -06:00			`# Benchmark "example_2.bench" written by ABC on Wed Nov 14 11:42:18 2018`
Addition of the second example and a ReadME to understand them. Also: - Figures were added 2018-10-09 15:42:15 -05:00			`.model example_2.bench`
			`.inputs I0 clk`
			`.outputs Q0`

Update of the examples to correspond to the new syntax 2018-11-14 15:01:39 -06:00			`.latch n7 Q0 re clk 0`
Addition of the second example and a ReadME to understand them. Also: - Figures were added 2018-10-09 15:42:15 -05:00
Update of the examples to correspond to the new syntax 2018-11-14 15:01:39 -06:00			`.names I0 n7`
Addition of the second example and a ReadME to understand them. Also: - Figures were added 2018-10-09 15:42:15 -05:00			`0 1`
Update of the examples to correspond to the new syntax 2018-11-14 15:01:39 -06:00			`.end`