OpenFPGA/ERI_demo/pipelined_8b_adder.blif

# Benchmark pipelined_32b_adder
.model pipelined_32b_adder
.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6]
.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7]

# Start pipeline
# Pipeline a
.subckt shift D=a[0] clk=clk Q=a_st0[0]
.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
.subckt shift D=a[1] clk=clk Q=a_st0[1]
.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
.subckt shift D=a[2] clk=clk Q=a_st0[2]
.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
.subckt shift D=a[3] clk=clk Q=a_st0[3]
.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
.subckt shift D=a[4] clk=clk Q=a_st0[4]
.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
.subckt shift D=a[5] clk=clk Q=a_st0[5]
.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
.subckt shift D=a[6] clk=clk Q=a_st0[6]
.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]

# Pipeline b
.subckt shift D=b[0] clk=clk Q=b_st0[0]
.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
.subckt shift D=b[1] clk=clk Q=b_st0[1]
.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
.subckt shift D=b[2] clk=clk Q=b_st0[2]
.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
.subckt shift D=b[3] clk=clk Q=b_st0[3]
.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
.subckt shift D=b[4] clk=clk Q=b_st0[4]
.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
.subckt shift D=b[5] clk=clk Q=b_st0[5]
.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
.subckt shift D=b[6] clk=clk Q=b_st0[6]
.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]

# Pipeline waddr
.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0]
.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1]
.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1]
.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2]
.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2]
.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3]
.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3]
.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4]
.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
# Pipeline wen
.subckt shift D=wen clk=clk Q=wen_st0
.subckt shift D=wen_st0 clk=clk Q=wen_st1
# End pipeline

# Start adder
.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7]
# End adder

# Start DPRAM
.subckt dpram clk=clk wen=wen_st1 ren=ren \
waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \
raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \
d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
d_in[30]=zero00 d_in[31]=zero00 \
d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \
d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn
# End DPRAM

# Start global variable
.names zero00
0
# End global variable


.end

# Start blackbox definition
.model dpram
.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
 waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \
 raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
 d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
 d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
 d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
 d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \
 d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \
 d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \
 d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \
 d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63]
.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
 d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
 d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
 d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
 d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \
 d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \
 d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \
 d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \
 d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \
 d_out[63]
.blackbox
.end


.model adder
.inputs a b cin
.outputs cout sumout
.blackbox
.end


.model shift
.inputs D clk
.outputs Q
.blackbox
.end
# End blackbox definition