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OpenFPGA/libs/librtlnumber/regression_tests/basic_regression_tests.csv

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add vpr8 libs and core engine for further integration
2020-01-03 17:14:42 -06:00
#####################
# Aaron Graham (aaron.graham@unb.ca, aarongraham9@gmail.com),
# Jean-Philippe Legault (jlegault@unb.ca, jeanphilippe.legault@gmail.com),
# Alexandrea Demmings (alexandrea.demmings@unb.ca, lxdemmings@gmail.com) and
# Dr. Kenneth B. Kent (ken@unb.ca)
# for the Reconfigurable Computing Research Lab at the
# Univerity of New Brunswick in Fredericton, New Brunswick, Canada
#####################
# truth test
simple_true, is_true, 1'b1, pass
simple_fail, is_true, 1'b0, fail
decimal_true, is_true, 1, pass
decimal_fail, is_true, 0, fail
complex_true, is_true, 2'b1x, pass
complex_fail, is_true, 2'b0x, fail
unknown_x, is_true, 1'bx, fail
large_number_pass, is_true, 128'h8000_0000_0000_0000, pass
# type test
simple_x_pass, is_x, 1'bx, pass
simple_x_fail, is_x, 1'b1, fail
simple_z_pass, is_z, 1'bz, pass
simple_z_fail, is_z, 1'b1, fail
simple_unk_pass, is_unk, 2'b1x, pass
simple_unk_fail, is_unk, 2'b11, fail
# sign test
simple_is_unsigned_pass, is_unsigned, 2'b11, pass
simple_is_unsigned_fail, is_unsigned, 2'sb11, fail
simple_is_signed_pass, is_signed, 2'b11, fail
simple_is_signed_fail, is_signed, 2'sb11, pass
# type conversion test
simple_is_unsigned_1, to_unsigned, 2'b11, 2'b11
simple_is_unsigned_2, to_unsigned, 2'sb11, 2'b11
simple_is_signed_1, to_signed, 2'b11, 2'sb11
simple_is_signed_2, to_signed, 2'sb11, 2'sb11
# string test
simple_string, display, "hello world", hello world
string_compare_pass, "hello world", ==, "hello world", 1'b1
string_compare_fail, "hello world", ==, "hello", 1'b0
string_ne_pass, "hello world", !=, "hello", 1'b1
string_ne_fail, "hello world", !=, "hello world", 1'b0
string_add, "a", +, 1, "b"
string_add_empty, "b", +, "", "b"
# replicate test
simple_replicate, {, 3, {, 2'b10, }, }, 6'b101010
# concat test
simple_concat, {, 2'b01, \, , 2'b10, }, 4'b0110
# base conversions
Decimal-To-Binary, 10, ==, 4'b1010, 1'b1
Binary-To-Decimal, 4'b1100, ==, 12, 1'b1
Decimal-To-Hex, 10, ==, 'hA, 1'b1
Hex-To-Decimal, 'hBF, ==, 191, 1'b1
Decimal-To-Octal, 10, ==, 'o12, 1'b1
Octal-To-Decimal, 'o37, ==, 31, 1'b1
# Sign modifier
Sign_minus, -, 10'b1010101010, 'b0101010110
Sign_plus, +, 4'b1010, 'b1010
# Simple Base 10 conversion
simple_decimal_conversion, +, 6, 6
simple_decimal_minus, 6, -, 1, 5
simple_decimal_plus, 6, +, 1, 7
simple_decimal_shift_right, 6, >>>, 1, 3
simple_decimal_shift_left, 6, <<<, 1, 12
# Reduction
Reduction-and, &, 4'b1010, 1'b0
Reduction-or, |, 4'b1010, 1'b1
Reduction-xor, ^, 4'b1010, 1'b0
Reduction-nand, ~&, 4'b1010, 1'b1
Reduction-nor, ~|, 4'b1010, 1'b1
Reduction-xnor, ~^, 4'b1010, 1'b1
# bitwise
Bitwise-Not, ~, 4'b1010, 'b0101
Bitwise-And, 4'b1010, &, 4'b1000, 'b1000
Bitwise-Or, 5'b1010, |, 5'b1000, 'b1010
Bitwise-Nor, 5'b1010, ~|, 5'b1000, 5'b10101
Bitwise-Nand, 5'b1010, ~&, 5'b1000, 5'b10111
Bitwise-Xnor, 5'b1010, ~^, 5'b1000, 5'b11101
Bitwise-Xor, 5'b1010, ^, 5'b1000, 2'b10
# case equivalence
Case-eq, 4'b1x10, ===, 4'b1x10, 1'b1
Case-ne, 4'b1x11, !==, 4'b1x10, 1'b1
Case-ne, 4'b1x10, !==, 4'b1x10, 1'b0
Case-eq, 4'b1x11, ===, 4'b1x10, 1'b0
# logical operation
Logical-Not, !, 4'b1010, 1'b0
Logical-And, 4'b1010, &&, 4'b1000, 1'b1
Logical-Or, 4'b1010, ||, 4'b1000, 1'b1
Logical-Or, 4'b0000, ||, 4'b1000, 1'b1
Logical-Or, 4'b0000, ||, 4'b0000, 1'b0
Logical-less, 4'b0000, <, 4'b0000, 1'b0
Logical-less-1, 4'b0000, <, 4'b0001, 1'b1
Logical-less-2, 4'b0001, <, 4'b0000, 1'b0
Logical-less-3, 4'bxxxx, <, 4'b0001, 1'bx
Logical-less-4, 4'b0001, <, 4'bxxxx, 1'bx
Logical-less-5, 4'b0xxx, <, 4'b1001, 1'b1
Logical-less-6, 4'b1001, <, 4'b0xxx, 1'b0
Logical-less-7, 4'sb1001, <, 4'sb0xxx, 1'b1
Logical-less-8, 4'sb0xxx, <, 4'sb1001, 1'b0
Logical-greater, 4'b0000, >, 4'b0000, 1'b0
Logical-greater-1, 4'b0000, >, 4'b0001, 1'b0
Logical-greater-2, 4'b0001, >, 4'b0000, 1'b1
Logical-greater-3, 4'bxxxx, >, 4'b0001, 1'bx
Logical-greater-4, 4'b0001, >, 4'bxxxx, 1'bx
Logical-greater-5, 4'b0xxx, >, 4'b1001, 1'b0
Logical-greater-6, 4'b1001, >, 4'b0xxx, 1'b1
Logical-greater-7, 4'sb1001, >, 4'sb0xxx, 1'b0
Logical-greater-8, 4'sb0xxx, >, 4'sb1001, 1'b1
Logical-gr-equal, 4'b0000, >=, 4'b0000, 1'b1
Logical-gr-equal-1, 4'b0000, >=, 4'b0001, 1'b0
Logical-gr-equal-2, 4'b0001, >=, 4'b0000, 1'b1
Logical-gr-equal-3, 4'bxxxx, >=, 4'b0001, 1'bx
Logical-gr-equal-4, 4'b0001, >=, 4'bxxxx, 1'bx
Logical-less-equal, 4'b0000, <=, 4'b0000, 1'b1
Logical-less-equal-1, 4'b0000, <=, 4'b0001, 1'b1
Logical-less-equal-2, 4'b0001, <=, 4'b0000, 1'b0
Logical-less-equal-3, 4'bxxxx, <=, 4'b0001, 1'bx
Logical-less-equal-4, 4'b0001, <=, 4'bxxxx, 1'bx
Logical-equal, 4'b0000, ==, 4'b0000, 1'b1
Logical-equal-1, 4'b0000, ==, 4'b0001, 1'b0
Logical-equal-2, 4'b0001, ==, 4'b0000, 1'b0
Logical-equal-3, 4'bxxxx, ==, 4'b0001, 1'bx
Logical-equal-4, 4'b0001, ==, 4'bxxxx, 1'bx
Logical-bits, 'b1110, ==, 4'b1110, 1'b1
Logical-not-equal, 4'b0000, !=, 4'b0000, 1'b0
Logical-not-equal-1, 4'b0000, !=, 4'b0001, 1'b1
Logical-not-equal-2, 4'b0001, !=, 4'b0000, 1'b1
Logical-not-equal-3, 4'bxxxx, !=, 4'b0001, 1'bx
Logical-not-equal-4, 4'b0001, !=, 4'bxxxx, 1'bx
# shift operation
Shift-left, 5'b00100, <<, 2'b10, 5'b10000
Shift-right, 5'b00100, >>, 2'b10, 1'b1
Signed-shift-left, 5'b00100, <<<, 2'b10, 5'b10000
Unsigned-Signed-shift-right, 5'b10100, >>>, 2'b10, 5'b00101
Signed-shift-right, 5'sb10100, >>>, 2'b10, 5'sb11101
# arithmetic
Addition, 4'b0110, +, 4'b0011, 'b1001
Addition-Base-10, 2, +, 2, 4
Subtraction, 4'b0100, -, 4'b0010, 'b10
Subtraction-Base-10, 4, -, 2, 2
Subtraction-Smaller-Larger, 4'b0010, -, 4'b0100, 4'b1110
Subtraction-Small-Base-10, 2, -, 4, 3'sb110
Division, 4'b1010, /, 4'b0010, 'b101
Division-Base-10, 10, /, 5, 2
Division-Neg, 4'sb1010, /, 3'sb010, 3'sb101
Multiplication, 4'b0010, *, 4'b0010, 'b100
Multiplication-Base-10, 2, *, 3, 6
Multiplication-Neg, 4, *, 4'sb1100, 7'sb1110000
Modulo, 4'b1011, %, 4'b0010, 'b1
Modulo-Base-10, 13, %, 5, 3
Modulo-Neg, 4'sb1011, %, 4'sb0010, 2'sb11
Power, 2'b10, **, 2'b10, 4'b0100
Power-Base-10, 2, **, 3, 8
Power-Zero, 4'b0010, **, 4'b0000, 'b1
Power-Zero-Base-10, 3, **, 0, 1
Power-Unknown, 4'b0000, **, 4'sb1110, 2'sbxx
Power-Neg-Even, 4'sb1111, **, 2'b10, 'b1
Power-Neg-Odd, 4'sb1111, **, 3'b011, 2'sb11
# Ternary operations
Ternary, 1'b1, ?, 2'b01, :, 2'b10, 2'b01
# Test Cases As-Per Verilog 2005 Specification:
# Page 46 "Table 5-8 Examples of modulus and power operators"
V2005-1, 10, %, 3, 1 # 10/3 yields a remainder of 1.
V2005-2, 11, %, 3, 2 # 11/3 yields a remainder of 2.
V2005-3, 12, %, 3, 0 # 12/3 yields no remainder.
V2005-4, 5'sb10110, %, 3'sb011, 2'sb11 # The result takes the sign of the first operand.
V2005-5, 11, %, 3'sb101, 2 # The result takes the sign of the first operand
#V2005-6, 5'sb10100, %, 3, 1 # -4'd12 is seen as a large positive number that leaves a remainder of 1 when divided by 3.
V2005-7, 3, **, 2, 9 # 3 * 3
V2005-8, 2, **, 3, 8 # 2 * 2 * 2
V2005-9, 2, **, 0, 1 # Anything to the zero exponent is 1.
V2005-10, 0, **, 0, 1 # Zero to the zero exponent is also 1.
V2005-11, 2, **, 3'sb111, 0 # 2 ** -1 = 1/2. Integer division truncates to zero.
V2005-12, 0, **, 2'sb11, 2'sbxx # 0 ** -1 = 1/0. Integer division by zero is 'bx.
#2.0 ** -3'sb1 0.5 2.0 is real, giving real reciprocal.
#9 ** 0.5 3.0 Real square root.
#9.0 ** (1/2) 1.0 Integer division truncates exponent to zero.
#-3.0 ** 2.0 9.0 Defined because real 2.0 is still integral value