136 lines
4.3 KiB
C++
136 lines
4.3 KiB
C++
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DffinitPass : public Pass {
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DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" dffinit [options] [selection]\n");
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log("\n");
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log("This pass sets an FF cell parameter to the the initial value of the net it\n");
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log("drives. (This is primarily used in FPGA flows.)\n");
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log("\n");
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log(" -ff <cell_name> <output_port> <init_param>\n");
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log(" operate on the specified cell type. this option can be used\n");
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log(" multiple times.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
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dict<IdString, dict<IdString, IdString>> ff_types;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-ff" && argidx+3 < args.size()) {
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IdString cell_name = RTLIL::escape_id(args[++argidx]);
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IdString output_port = RTLIL::escape_id(args[++argidx]);
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IdString init_param = RTLIL::escape_id(args[++argidx]);
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ff_types[cell_name][output_port] = init_param;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, State> init_bits;
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pool<SigBit> cleanup_bits;
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pool<SigBit> used_bits;
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for (auto wire : module->selected_wires()) {
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if (wire->attributes.count("\\init")) {
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Const value = wire->attributes.at("\\init");
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for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
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init_bits[sigmap(SigBit(wire, i))] = value[i];
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}
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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used_bits.insert(bit);
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}
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for (auto cell : module->selected_cells())
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{
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for (auto it : cell->connections())
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if (!cell->known() || cell->input(it.first))
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for (auto bit : sigmap(it.second))
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used_bits.insert(bit);
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if (ff_types.count(cell->type) == 0)
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continue;
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for (auto &it : ff_types[cell->type])
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{
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if (!cell->hasPort(it.first))
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continue;
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SigSpec sig = sigmap(cell->getPort(it.first));
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Const value;
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if (cell->hasParam(it.second))
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value = cell->getParam(it.second);
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for (int i = 0; i < GetSize(sig); i++) {
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if (init_bits.count(sig[i]) == 0)
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continue;
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while (GetSize(value.bits) <= i)
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value.bits.push_back(State::S0);
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value.bits[i] = init_bits.at(sig[i]);
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cleanup_bits.insert(sig[i]);
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}
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log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),
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log_id(it.first), log_signal(sig), log_signal(value));
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cell->setParam(it.second, value);
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}
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}
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for (auto wire : module->selected_wires())
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if (wire->attributes.count("\\init")) {
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Const &value = wire->attributes.at("\\init");
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bool do_cleanup = true;
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for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
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SigBit bit = sigmap(SigBit(wire, i));
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if (cleanup_bits.count(bit) || !used_bits.count(bit))
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value[i] = State::Sx;
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else if (value[i] != State::Sx)
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do_cleanup = false;
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}
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if (do_cleanup) {
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log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
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wire->attributes.erase("\\init");
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}
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}
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}
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}
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} DffinitPass;
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PRIVATE_NAMESPACE_END
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