OpenFPGA/yosys/manual/presentation.tex

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\title{Yosys Open SYnthesis Suite}
\author{Clifford Wolf}
\institute{http://www.clifford.at/yosys/}

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\begin{document}

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\titlepage
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\setcounter{section}{-3}

\section{Abstract}
\begin{frame}{Abstract}
Yosys is the first full-featured open source software for Verilog HDL
synthesis. It supports most of Verilog-2005 and is well tested with
real-world designs from the ASIC and FPGA world.

\bigskip
Learn how to use Yosys to create your own custom synthesis flows and
discover why open source HDL synthesis is important for researchers,
hobbyists, educators and engineers alike.

\bigskip
This presentation covers basic concepts of Yosys, writing synthesis scripts
for a wide range of applications, creating Yosys scripts for various
non-synthesis applications (such as formal equivalence checking) and
writing extensions to Yosys using the C++ API.
\end{frame}

\section{About me}
\begin{frame}{About me}
Hi! I'm Clifford Wolf.

\bigskip
I like writing open source software. For example:
\begin{itemize}
\item Yosys
\item OpenSCAD (now maintained by Marius Kintel)
\item SPL (a not very popular scripting language)
\item EmbedVM (a very simple compiler+vm for 8 bit micros)
\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG)
\item ROCK Linux (discontinued since 2010)
\end{itemize}
\end{frame}

\section{Outline}
\begin{frame}{Outline}
Yosys is an Open Source Verilog synthesis tool, and more.

\bigskip
Outline of this presentation:
\begin{itemize}
\item Introduction to the field and Yosys
\item Yosys by example: synthesis
\item Yosys by example: advanced synthesis
\item Yosys by example: beyond synthesis
\item Writing Yosys extensions in C++
\end{itemize}
\end{frame}

\include{PRESENTATION_Intro}
\include{PRESENTATION_ExSyn}
\include{PRESENTATION_ExAdv}
\include{PRESENTATION_ExOth}
\include{PRESENTATION_Prog}

\end{document}