85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef COST_H
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#define COST_H
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#include <kernel/yosys.h>
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YOSYS_NAMESPACE_BEGIN
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int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr);
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int get_cell_cost(RTLIL::IdString type, const dict<RTLIL::IdString, RTLIL::Const> ¶meters = dict<RTLIL::IdString, RTLIL::Const>(),
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RTLIL::Design *design = nullptr, dict<RTLIL::IdString, int> *mod_cost_cache = nullptr)
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{
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static dict<RTLIL::IdString, int> gate_cost = {
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{ "$_BUF_", 1 },
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{ "$_NOT_", 2 },
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{ "$_AND_", 4 },
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{ "$_NAND_", 4 },
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{ "$_OR_", 4 },
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{ "$_NOR_", 4 },
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{ "$_XOR_", 8 },
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{ "$_XNOR_", 8 },
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{ "$_AOI3_", 6 },
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{ "$_OAI3_", 6 },
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{ "$_AOI4_", 8 },
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{ "$_OAI4_", 8 },
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{ "$_MUX_", 4 }
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};
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if (gate_cost.count(type))
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return gate_cost.at(type);
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if (parameters.empty() && design && design->module(type))
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{
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RTLIL::Module *mod = design->module(type);
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if (mod->attributes.count("\\cost"))
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return mod->attributes.at("\\cost").as_int();
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dict<RTLIL::IdString, int> local_mod_cost_cache;
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if (mod_cost_cache == nullptr)
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mod_cost_cache = &local_mod_cost_cache;
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if (mod_cost_cache->count(mod->name))
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return mod_cost_cache->at(mod->name);
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int module_cost = 1;
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for (auto c : mod->cells())
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module_cost += get_cell_cost(c, mod_cost_cache);
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(*mod_cost_cache)[mod->name] = module_cost;
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return module_cost;
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}
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log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
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return 1;
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}
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int get_cell_cost(RTLIL::Cell *cell, dict<RTLIL::IdString, int> *mod_cost_cache)
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{
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return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache);
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}
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YOSYS_NAMESPACE_END
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#endif
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