2020-07-05 13:10:12 -05:00
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/*********************************************************************
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* This file includes top-level function to generate Spice primitive modules
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* and print them to files
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********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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2020-07-05 15:50:29 -05:00
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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2020-07-05 13:10:12 -05:00
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#include "spice_essential_gates.h"
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#include "spice_constants.h"
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#include "spice_submodule.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Top-level function to generate primitive modules:
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* 1. Transistor wrapper
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* 2. TODO: Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
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* 3. TODO: Routing multiplexers
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* 4. TODO: Local encoders for routing multiplexers
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* 5. TODO: Wires
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* 6. TODO: Configuration memory blocks
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********************************************************************/
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2020-07-05 15:50:29 -05:00
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int print_spice_submodule(NetlistManager& netlist_manager,
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const TechnologyLibrary& tech_lib,
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const std::string& submodule_dir) {
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int status = CMD_EXEC_SUCCESS;
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status = print_spice_transistor_wrapper(netlist_manager,
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tech_lib,
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submodule_dir);
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2020-07-05 13:10:12 -05:00
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2020-07-05 15:50:29 -05:00
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return status;
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2020-07-05 13:10:12 -05:00
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}
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} /* end namespace openfpga */
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